1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
11 #include <asm/u-boot.h>
12 #include <asm/utils.h>
14 #include <debug_uart.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/firewall.h>
19 #include <asm/arch/mailbox_s10.h>
20 #include <asm/arch/misc.h>
21 #include <asm/arch/reset_manager.h>
22 #include <asm/arch/system_manager.h>
24 #include <dm/uclass.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 u32 spl_boot_device(void)
30 /* TODO: Get from SDM or handoff */
31 return BOOT_DEVICE_MMC1;
34 #ifdef CONFIG_SPL_MMC_SUPPORT
35 u32 spl_mmc_boot_mode(const u32 boot_device)
37 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
40 return MMCSD_MODE_RAW;
45 void board_init_f(ulong dummy)
47 const struct cm_config *cm_default_cfg = cm_get_default_config();
50 ret = spl_early_init();
54 socfpga_get_managers_addr();
56 /* Ensure watchdog is paused when debugging is happening */
57 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
58 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
60 #ifdef CONFIG_HW_WATCHDOG
61 /* Enable watchdog before initializing the HW */
62 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
63 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
67 /* ensure all processors are not released prior Linux boot */
68 writeq(0, CPU_RELEASE_ADDR);
70 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
75 /* configuring the HPS clocks */
76 cm_basic_init(cm_default_cfg);
78 #ifdef CONFIG_DEBUG_UART
79 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
83 preloader_console_init();
85 cm_print_clock_quick_summary();
89 /* disable ocram security at CCU for non secure access */
90 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
91 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
92 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
93 CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
95 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
98 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
100 debug("DRAM init failed: %d\n", ret);
107 #ifdef CONFIG_CADENCE_QSPI