1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
9 #include <asm/u-boot.h>
10 #include <asm/utils.h>
12 #include <asm/arch/reset_manager.h>
14 #include <asm/arch/system_manager.h>
15 #include <asm/arch/freeze_controller.h>
16 #include <asm/arch/clock_manager.h>
17 #include <asm/arch/misc.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/sections.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 static struct pl310_regs *const pl310 =
29 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30 static struct scu_registers *scu_regs =
31 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
32 static struct nic301_registers *nic301_regs =
33 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
34 static const struct socfpga_system_manager *sysmgr_regs =
35 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
37 u32 spl_boot_device(void)
39 const u32 bsel = readl(&sysmgr_regs->bootinfo);
41 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
42 case 0x1: /* FPGA (HPS2FPGA Bridge) */
43 return BOOT_DEVICE_RAM;
44 case 0x2: /* NAND Flash (1.8V) */
45 case 0x3: /* NAND Flash (3.0V) */
46 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
47 return BOOT_DEVICE_NAND;
48 case 0x4: /* SD/MMC External Transceiver (1.8V) */
49 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
50 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
51 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
52 return BOOT_DEVICE_MMC1;
53 case 0x6: /* QSPI Flash (1.8V) */
54 case 0x7: /* QSPI Flash (3.0V) */
55 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
56 return BOOT_DEVICE_SPI;
58 printf("Invalid boot device (bsel=%08x)!\n", bsel);
63 #ifdef CONFIG_SPL_MMC_SUPPORT
64 u32 spl_boot_mode(const u32 boot_device)
66 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
69 return MMCSD_MODE_RAW;
74 static void socfpga_nic301_slave_ns(void)
76 writel(0x1, &nic301_regs->lwhps2fpgaregs);
77 writel(0x1, &nic301_regs->hps2fpgaregs);
78 writel(0x1, &nic301_regs->acp);
79 writel(0x1, &nic301_regs->rom);
80 writel(0x1, &nic301_regs->ocram);
81 writel(0x1, &nic301_regs->sdrdata);
84 void board_init_f(ulong dummy)
86 const struct cm_config *cm_default_cfg = cm_get_default_config();
87 unsigned long sdram_size;
92 * First C code to run. Clear fake OCRAM ECC first as SBE
93 * and DBE might triggered during power on
95 reg = readl(&sysmgr_regs->eccgrp_ocram);
96 if (reg & SYSMGR_ECC_OCRAM_SERR)
97 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
98 &sysmgr_regs->eccgrp_ocram);
99 if (reg & SYSMGR_ECC_OCRAM_DERR)
100 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
101 &sysmgr_regs->eccgrp_ocram);
103 memset(__bss_start, 0, __bss_end - __bss_start);
105 socfpga_nic301_slave_ns();
107 /* Configure ARM MPU SNSAC register. */
108 setbits_le32(&scu_regs->sacr, 0xfff);
110 /* Remap SDRAM to 0x0 */
111 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
112 writel(0x1, &pl310->pl310_addr_filter_start);
114 debug("Freezing all I/O banks\n");
115 /* freeze all IO banks */
116 sys_mgr_frzctrl_freeze_req();
118 /* Put everything into reset but L4WD0. */
119 socfpga_per_reset_all();
120 /* Put FPGA bridges into reset too. */
121 socfpga_bridges_reset(1);
123 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
124 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
125 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
129 debug("Reconfigure Clock Manager\n");
130 /* reconfigure the PLLs */
131 if (cm_basic_init(cm_default_cfg))
134 /* Enable bootrom to configure IOs. */
135 sysmgr_config_warmrstcfgio(1);
137 /* configure the IOCSR / IO buffer settings */
138 if (scan_mgr_configure_iocsr())
141 sysmgr_config_warmrstcfgio(0);
143 /* configure the pin muxing through system manager */
144 sysmgr_config_warmrstcfgio(1);
145 sysmgr_pinmux_init();
146 sysmgr_config_warmrstcfgio(0);
148 /* De-assert reset for peripherals and bridges based on handoff */
149 reset_deassert_peripherals_handoff();
150 socfpga_bridges_reset(0);
152 debug("Unfreezing/Thaw all I/O banks\n");
153 /* unfreeze / thaw all IO banks */
154 sys_mgr_frzctrl_thaw_req();
156 ret = spl_early_init();
158 debug("spl_early_init() failed: %d\n", ret);
162 /* enable console uart printing */
163 preloader_console_init();
165 if (sdram_mmr_init_full(0xffffffff) != 0) {
166 puts("SDRAM init failed.\n");
170 debug("SDRAM: Calibrating PHY\n");
171 /* SDRAM calibration */
172 if (sdram_calibration_full() == 0) {
173 puts("SDRAM calibration failed.\n");
177 sdram_size = sdram_calculate_size();
178 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
180 /* Sanity check ensure correct SDRAM size specified */
181 if (get_ram_size(0, sdram_size) != sdram_size) {
182 puts("SDRAM size check failed!\n");
186 socfpga_bridges_reset(1);