1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
16 #include <asm/arch/clock_manager.h>
17 #include <asm/arch/firewall.h>
18 #include <asm/arch/mailbox_s10.h>
19 #include <asm/arch/misc.h>
20 #include <asm/arch/reset_manager.h>
21 #include <asm/arch/system_manager.h>
23 #include <dm/uclass.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 u32 spl_boot_device(void)
29 return BOOT_DEVICE_MMC1;
32 #ifdef CONFIG_SPL_MMC_SUPPORT
33 u32 spl_mmc_boot_mode(const u32 boot_device)
35 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
38 return MMCSD_MODE_RAW;
43 void board_init_f(ulong dummy)
48 ret = spl_early_init();
52 socfpga_get_managers_addr();
54 /* Ensure watchdog is paused when debugging is happening */
55 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
56 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
58 #ifdef CONFIG_HW_WATCHDOG
59 /* Enable watchdog before initializing the HW */
60 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
61 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
65 /* ensure all processors are not released prior Linux boot */
66 writeq(0, CPU_RELEASE_ADDR);
72 ret = uclass_get_device(UCLASS_CLK, 0, &dev);
74 debug("Clock init failed: %d\n", ret);
78 preloader_console_init();
80 cm_print_clock_quick_summary();
83 ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
85 debug("CCU init failed: %d\n", ret);
89 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
90 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
92 debug("DRAM init failed: %d\n", ret);
99 #ifdef CONFIG_CADENCE_QSPI