arch/arm/mach-socfpga/spl_agilex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <init.h>
   8 #include <log.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/u-boot.h>
  12 #include <asm/utils.h>
  13 #include <common.h>
  14 #include <hang.h>
  15 #include <image.h>
  16 #include <spl.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/firewall.h>
  19 #include <asm/arch/mailbox_s10.h>
  20 #include <asm/arch/misc.h>
  21 #include <asm/arch/reset_manager.h>
  22 #include <asm/arch/system_manager.h>
  23 #include <watchdog.h>
  24 #include <dm/uclass.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 void board_init_f(ulong dummy)
  29 {
  30         int ret;
  31         struct udevice *dev;
  32
  33         ret = spl_early_init();
  34         if (ret)
  35                 hang();
  36
  37         socfpga_get_managers_addr();
  38
  39         /* Ensure watchdog is paused when debugging is happening */
  40         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  41                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  42
  43 #ifdef CONFIG_HW_WATCHDOG
  44         /* Enable watchdog before initializing the HW */
  45         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  46         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  47         hw_watchdog_init();
  48 #endif
  49
  50         /* ensure all processors are not released prior Linux boot */
  51         writeq(0, CPU_RELEASE_ADDR);
  52
  53         timer_init();
  54
  55         sysmgr_pinmux_init();
  56
  57         ret = uclass_get_device(UCLASS_CLK, 0, &dev);
  58         if (ret) {
  59                 debug("Clock init failed: %d\n", ret);
  60                 hang();
  61         }
  62
  63         preloader_console_init();
  64         print_reset_info();
  65         cm_print_clock_quick_summary();
  66
  67         firewall_setup();
  68         ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
  69         if (ret) {
  70                 debug("CCU init failed: %d\n", ret);
  71                 hang();
  72         }
  73
  74 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  75         ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  76         if (ret) {
  77                 debug("DRAM init failed: %d\n", ret);
  78                 hang();
  79         }
  80 #endif
  81
  82         mbox_init();
  83
  84 #ifdef CONFIG_CADENCE_QSPI
  85         mbox_qspi_open();
  86 #endif
  87 }