1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
11 #include <asm/pl310.h>
12 #include <asm/u-boot.h>
13 #include <asm/utils.h>
15 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/system_manager.h>
18 #include <asm/arch/freeze_controller.h>
19 #include <asm/arch/clock_manager.h>
20 #include <asm/arch/scan_manager.h>
21 #include <asm/arch/sdram.h>
22 #include <asm/arch/scu.h>
23 #include <asm/arch/misc.h>
24 #include <asm/arch/nic301.h>
25 #include <asm/sections.h>
28 #include <asm/arch/pinmux.h>
29 #include <asm/arch/fpga_manager.h>
33 #define FPGA_BUFSIZ 16 * 1024
35 DECLARE_GLOBAL_DATA_PTR;
37 #define BOOTROM_SHARED_MEM_SIZE 0x800 /* 2KB */
38 #define BOOTROM_SHARED_MEM_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
39 SOCFPGA_PHYS_OCRAM_SIZE - \
40 BOOTROM_SHARED_MEM_SIZE)
41 #define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
42 static u32 rst_mgr_status __section(.data);
45 * Bootrom will clear the status register in reset manager and stores the
46 * reset status value in shared memory. Bootrom stores shared data at last
48 * This function save reset status provided by BootROM to rst_mgr_status.
49 * More information about reset status register value can be found in reset
50 * manager register description.
51 * When running in debugger without Bootrom, r0 to r3 are random values.
52 * So, skip save the value when r0 is not BootROM shared data address.
54 * r0 - Contains the pointer to the shared memory block. The shared
55 * memory block is located in the top 2 KB of on-chip RAM.
56 * r1 - contains the length of the shared memory.
57 * r2 - unused and set to 0x0.
58 * r3 - points to the version block.
60 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
63 if (r0 == BOOTROM_SHARED_MEM_ADDR)
64 rst_mgr_status = readl(RST_STATUS_SHARED_ADDR);
66 save_boot_params_ret();
69 u32 spl_boot_device(void)
71 const u32 bsel = readl(socfpga_get_sysmgr_addr() + SYSMGR_A10_BOOTINFO);
73 switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
74 case 0x1: /* FPGA (HPS2FPGA Bridge) */
75 return BOOT_DEVICE_RAM;
76 case 0x2: /* NAND Flash (1.8V) */
77 case 0x3: /* NAND Flash (3.0V) */
78 socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
79 return BOOT_DEVICE_NAND;
80 case 0x4: /* SD/MMC External Transceiver (1.8V) */
81 case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
82 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
83 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
84 return BOOT_DEVICE_MMC1;
85 case 0x6: /* QSPI Flash (1.8V) */
86 case 0x7: /* QSPI Flash (3.0V) */
87 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
88 return BOOT_DEVICE_SPI;
90 printf("Invalid boot device (bsel=%08x)!\n", bsel);
95 #ifdef CONFIG_SPL_MMC_SUPPORT
96 u32 spl_mmc_boot_mode(const u32 boot_device)
98 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
101 return MMCSD_MODE_RAW;
106 void spl_board_init(void)
108 ALLOC_CACHE_ALIGN_BUFFER(char, buf, FPGA_BUFSIZ);
110 /* enable console uart printing */
111 preloader_console_init();
116 /* If the full FPGA is already loaded, ie.from EPCQ, config fpga pins */
117 if (is_fpgamgr_user_mode()) {
118 int ret = config_pins(gd->fdt_blob, "shared");
123 ret = config_pins(gd->fdt_blob, "fpga");
126 } else if (!is_fpgamgr_early_user_mode()) {
127 /* Program IOSSM(early IO release) or full FPGA */
128 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
131 /* If the IOSSM/full FPGA is already loaded, start DDR */
132 if (is_fpgamgr_early_user_mode() || is_fpgamgr_user_mode())
133 ddr_calibration_sequence();
135 if (!is_fpgamgr_user_mode())
136 fpgamgr_program(buf, FPGA_BUFSIZ, 0);
139 void board_init_f(ulong dummy)
141 if (spl_early_init())
144 socfpga_get_managers_addr();
148 socfpga_init_security_policies();
149 socfpga_sdram_remap_zero();
150 socfpga_pl310_clear();
152 /* Assert reset to all except L4WD0 and L4TIMER0 */
153 socfpga_per_reset_all();
154 socfpga_watchdog_disable();
156 /* Configure the clock based on handoff */
157 cm_basic_init(gd->fdt_blob);
159 #ifdef CONFIG_HW_WATCHDOG
160 /* release osc1 watchdog timer 0 from reset */
161 socfpga_reset_deassert_osc1wd0();
163 /* reconfigure and enable the watchdog */
166 #endif /* CONFIG_HW_WATCHDOG */
168 config_dedicated_pins(gd->fdt_blob);