arch/arm/mach-socfpga/reset_manager_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <hang.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/reset_manager.h>
  12 #include <asm/arch/smc_api.h>
  13 #include <asm/arch/system_manager.h>
  14 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  15 #include <linux/iopoll.h>
  16 #include <linux/intel-smc.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* Assert or de-assert SoCFPGA reset manager reset. */
  21 void socfpga_per_reset(u32 reset, int set)
  22 {
  23         unsigned long reg;
  24
  25         if (RSTMGR_BANK(reset) == 0)
  26                 reg = RSTMGR_SOC64_MPUMODRST;
  27         else if (RSTMGR_BANK(reset) == 1)
  28                 reg = RSTMGR_SOC64_PER0MODRST;
  29         else if (RSTMGR_BANK(reset) == 2)
  30                 reg = RSTMGR_SOC64_PER1MODRST;
  31         else if (RSTMGR_BANK(reset) == 3)
  32                 reg = RSTMGR_SOC64_BRGMODRST;
  33         else    /* Invalid reset register, do nothing */
  34                 return;
  35
  36         if (set)
  37                 setbits_le32(socfpga_get_rstmgr_addr() + reg,
  38                              1 << RSTMGR_RESET(reset));
  39         else
  40                 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  41                              1 << RSTMGR_RESET(reset));
  42 }
  43
  44 /*
  45  * Assert reset on every peripheral but L4WD0.
  46  * Watchdog must be kept intact to prevent glitches
  47  * and/or hangs.
  48  */
  49 void socfpga_per_reset_all(void)
  50 {
  51         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  52
  53         /* disable all except OCP and l4wd0. OCP disable later */
  54         writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  55                       socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  56         writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  57         writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
  58 }
  59
  60 void socfpga_bridges_reset(int enable)
  61 {
  62 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
  63         u64 arg = enable;
  64
  65         int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
  66         if (ret) {
  67                 printf("SMC call failed with error %d in %s.\n", ret, __func__);
  68                 return;
  69         }
  70 #else
  71         u32 reg;
  72
  73         if (enable) {
  74                 /* clear idle request to all bridges */
  75                 setbits_le32(socfpga_get_sysmgr_addr() +
  76                              SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
  77
  78                 /* Release all bridges from reset state */
  79                 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  80                              ~0);
  81
  82                 /* Poll until all idleack to 0 */
  83                 read_poll_timeout(readl, reg, !reg, 1000, 300000,
  84                                   socfpga_get_sysmgr_addr() +
  85                                   SYSMGR_SOC64_NOC_IDLEACK);
  86         } else {
  87                 /* set idle request to all bridges */
  88                 writel(~0,
  89                        socfpga_get_sysmgr_addr() +
  90                        SYSMGR_SOC64_NOC_IDLEREQ_SET);
  91
  92                 /* Enable the NOC timeout */
  93                 writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  94
  95                 /* Poll until all idleack to 1 */
  96                 read_poll_timeout(readl, reg,
  97                                   reg == (SYSMGR_NOC_H2F_MSK |
  98                                           SYSMGR_NOC_LWH2F_MSK),
  99                                   1000, 300000,
 100                                   socfpga_get_sysmgr_addr() +
 101                                   SYSMGR_SOC64_NOC_IDLEACK);
 102
 103                 /* Poll until all idlestatus to 1 */
 104                 read_poll_timeout(readl, reg,
 105                                   reg == (SYSMGR_NOC_H2F_MSK |
 106                                           SYSMGR_NOC_LWH2F_MSK),
 107                                   1000, 300000,
 108                                   socfpga_get_sysmgr_addr() +
 109                                   SYSMGR_SOC64_NOC_IDLESTATUS);
 110
 111                 /* Reset all bridges (except NOR DDR scheduler & F2S) */
 112                 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
 113                              ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
 114                                RSTMGR_BRGMODRST_FPGA2SOC_MASK));
 115
 116                 /* Disable NOC timeout */
 117                 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 118         }
 119 #endif
 120 }
 121
 122 /*
 123  * Return non-zero if the CPU has been warm reset
 124  */
 125 int cpu_has_been_warmreset(void)
 126 {
 127         return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
 128                         RSTMGR_L4WD_MPU_WARMRESET_MASK;
 129 }
 130
 131 void print_reset_info(void)
 132 {
 133         bool iswd;
 134         int n;
 135         u32 stat = cpu_has_been_warmreset();
 136
 137         printf("Reset state: %s%s", stat ? "Warm " : "Cold",
 138                (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
 139
 140         stat &= ~RSTMGR_STAT_SDMWARMRST;
 141         if (!stat) {
 142                 puts("\n");
 143                 return;
 144         }
 145
 146         n = generic_ffs(stat) - 1;
 147         iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
 148         printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
 149                iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
 150                (n - RSTMGR_STAT_MPU0RST_BITPOS));
 151 }