arch/arm/mach-socfpga/reset_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <asm/io.h>
   7 #include <asm/arch/fpga_manager.h>
   8 #include <asm/arch/misc.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <wait_bit.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 static const struct socfpga_reset_manager *reset_manager_base =
  19                 (void *)SOCFPGA_RSTMGR_ADDRESS;
  20 static const struct socfpga_system_manager *sysmgr_regs =
  21                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  22
  23 #define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
  24         ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
  25         ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
  26         ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
  27         ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
  28         ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
  29
  30 static const u32 per0fpgamasks[] = {
  31         ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
  32         ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
  33         ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
  34         ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
  35         ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
  36         ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
  37         0, /* i2c0 per1mod */
  38         0, /* i2c1 per1mod */
  39         0, /* i2c0_emac */
  40         0, /* i2c1_emac */
  41         0, /* i2c2_emac */
  42         ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
  43         ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
  44         ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
  45         ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
  46         ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
  47         ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
  48         ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
  49         ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
  50         ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
  51         ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
  52         0, /* uart0 per1mod */
  53         0, /* uart1 per1mod */
  54 };
  55
  56 static const u32 per1fpgamasks[] = {
  57         0, /* emac0 per0mod */
  58         0, /* emac1 per0mod */
  59         0, /* emac2 per0mod */
  60         ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
  61         ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
  62         ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
  63         ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
  64         ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
  65         0, /* nand per0mod */
  66         0, /* qspi per0mod */
  67         0, /* sdmmc per0mod */
  68         0, /* spim0 per0mod */
  69         0, /* spim1 per0mod */
  70         0, /* spis0 per0mod */
  71         0, /* spis1 per0mod */
  72         ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
  73         ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
  74 };
  75
  76 struct bridge_cfg {
  77         int compat_id;
  78         u32  mask_noc;
  79         u32  mask_rstmgr;
  80 };
  81
  82 static const struct bridge_cfg bridge_cfg_tbl[] = {
  83         {
  84                 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
  85                 ALT_SYSMGR_NOC_H2F_SET_MSK,
  86                 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
  87         },
  88         {
  89                 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
  90                 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
  91                 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
  92         },
  93         {
  94                 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
  95                 ALT_SYSMGR_NOC_F2H_SET_MSK,
  96                 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
  97         },
  98         {
  99                 COMPAT_ALTERA_SOCFPGA_F2SDR0,
 100                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
 101                 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
 102         },
 103         {
 104                 COMPAT_ALTERA_SOCFPGA_F2SDR1,
 105                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
 106                 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
 107         },
 108         {
 109                 COMPAT_ALTERA_SOCFPGA_F2SDR2,
 110                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 111                 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
 112         },
 113 };
 114
 115 /* Disable the watchdog (toggle reset to watchdog) */
 116 void socfpga_watchdog_disable(void)
 117 {
 118         /* assert reset for watchdog */
 119         setbits_le32(&reset_manager_base->per1modrst,
 120                      ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 121 }
 122
 123 /* Release NOC ddr scheduler from reset */
 124 void socfpga_reset_deassert_noc_ddr_scheduler(void)
 125 {
 126         clrbits_le32(&reset_manager_base->brgmodrst,
 127                      ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
 128 }
 129
 130 /* Check whether Watchdog in reset state? */
 131 int socfpga_is_wdt_in_reset(void)
 132 {
 133         u32 val;
 134
 135         val = readl(&reset_manager_base->per1modrst);
 136         val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
 137
 138         /* return 0x1 if watchdog in reset */
 139         return val;
 140 }
 141
 142 /* emacbase: base address of emac to enable/disable reset
 143  * state: 0 - disable reset, !0 - enable reset
 144  */
 145 void socfpga_emac_manage_reset(ulong emacbase, u32 state)
 146 {
 147         ulong eccmask;
 148         ulong emacmask;
 149
 150         switch (emacbase) {
 151         case SOCFPGA_EMAC0_ADDRESS:
 152                 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
 153                 emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
 154                 break;
 155         case SOCFPGA_EMAC1_ADDRESS:
 156                 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
 157                 emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
 158                 break;
 159         case SOCFPGA_EMAC2_ADDRESS:
 160                 eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
 161                 emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
 162                 break;
 163         default:
 164                 pr_err("emac base address unexpected! %lx", emacbase);
 165                 hang();
 166                 break;
 167         }
 168
 169         if (state) {
 170                 /* Enable ECC OCP first */
 171                 setbits_le32(&reset_manager_base->per0modrst, eccmask);
 172                 setbits_le32(&reset_manager_base->per0modrst, emacmask);
 173         } else {
 174                 /* Disable ECC OCP first */
 175                 clrbits_le32(&reset_manager_base->per0modrst, emacmask);
 176                 clrbits_le32(&reset_manager_base->per0modrst, eccmask);
 177         }
 178 }
 179
 180 static int get_bridge_init_val(const void *blob, int compat_id)
 181 {
 182         int node;
 183
 184         node = fdtdec_next_compatible(blob, 0, compat_id);
 185         if (node < 0)
 186                 return 0;
 187
 188         return fdtdec_get_uint(blob, node, "init-val", 0);
 189 }
 190
 191 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
 192 int socfpga_reset_deassert_bridges_handoff(void)
 193 {
 194         u32 mask_noc = 0, mask_rstmgr = 0;
 195         int i;
 196
 197         for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
 198                 if (get_bridge_init_val(gd->fdt_blob,
 199                                         bridge_cfg_tbl[i].compat_id)) {
 200                         mask_noc |= bridge_cfg_tbl[i].mask_noc;
 201                         mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
 202                 }
 203         }
 204
 205         /* clear idle request to all bridges */
 206         setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
 207
 208         /* Release bridges from reset state per handoff value */
 209         clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
 210
 211         /* Poll until all idleack to 0, timeout at 1000ms */
 212         return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
 213                                  false, 1000, false);
 214 }
 215
 216 void socfpga_reset_assert_fpga_connected_peripherals(void)
 217 {
 218         u32 mask0 = 0;
 219         u32 mask1 = 0;
 220         u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
 221         int i;
 222
 223         for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
 224                 if (readl(fpga_pinux_addr)) {
 225                         mask0 |= per0fpgamasks[i];
 226                         mask1 |= per1fpgamasks[i];
 227                 }
 228                 fpga_pinux_addr += sizeof(u32);
 229         }
 230
 231         setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
 232         setbits_le32(&reset_manager_base->per1modrst, mask1);
 233         setbits_le32(&reset_manager_base->per0modrst, mask0);
 234 }
 235
 236 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 237 void socfpga_reset_deassert_osc1wd0(void)
 238 {
 239         clrbits_le32(&reset_manager_base->per1modrst,
 240                      ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 241 }
 242
 243 /*
 244  * Assert or de-assert SoCFPGA reset manager reset.
 245  */
 246 void socfpga_per_reset(u32 reset, int set)
 247 {
 248         const u32 *reg;
 249         u32 rstmgr_bank = RSTMGR_BANK(reset);
 250
 251         switch (rstmgr_bank) {
 252         case 0:
 253                 reg = &reset_manager_base->mpumodrst;
 254                 break;
 255         case 1:
 256                 reg = &reset_manager_base->per0modrst;
 257                 break;
 258         case 2:
 259                 reg = &reset_manager_base->per1modrst;
 260                 break;
 261         case 3:
 262                 reg = &reset_manager_base->brgmodrst;
 263                 break;
 264         case 4:
 265                 reg = &reset_manager_base->sysmodrst;
 266                 break;
 267
 268         default:
 269                 return;
 270         }
 271
 272         if (set)
 273                 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
 274         else
 275                 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
 276 }
 277
 278 /*
 279  * Assert reset on every peripheral but L4WD0.
 280  * Watchdog must be kept intact to prevent glitches
 281  * and/or hangs.
 282  * For the Arria10, we disable all the peripherals except L4 watchdog0,
 283  * L4 Timer 0, and ECC.
 284  */
 285 void socfpga_per_reset_all(void)
 286 {
 287         const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
 288                           (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
 289         unsigned mask_ecc_ocp =
 290                 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
 291                 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
 292                 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
 293                 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
 294                 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
 295                 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
 296                 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
 297                 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 298
 299         /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
 300         writel(~l4wd0, &reset_manager_base->per1modrst);
 301         setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
 302
 303         /* Finally disable the ECC_OCP */
 304         setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
 305 }
 306
 307 int socfpga_bridges_reset(void)
 308 {
 309         int ret;
 310
 311         /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
 312            fpga2sdram) */
 313         /* set idle request to all bridges */
 314         writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
 315                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 316                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 317                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 318                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 319                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 320                 &sysmgr_regs->noc_idlereq_set);
 321
 322         /* Enable the NOC timeout */
 323         writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
 324
 325         /* Poll until all idleack to 1 */
 326         ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
 327                                 ALT_SYSMGR_NOC_H2F_SET_MSK |
 328                                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 329                                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 330                                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 331                                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 332                                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 333                                 true, 10000, false);
 334         if (ret)
 335                 return ret;
 336
 337         /* Poll until all idlestatus to 1 */
 338         ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
 339                                 ALT_SYSMGR_NOC_H2F_SET_MSK |
 340                                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 341                                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 342                                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 343                                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 344                                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 345                                 true, 10000, false);
 346         if (ret)
 347                 return ret;
 348
 349         /* Put all bridges (except NOR DDR scheduler) into reset state */
 350         setbits_le32(&reset_manager_base->brgmodrst,
 351                      (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
 352                      ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
 353                      ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
 354                      ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
 355                      ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
 356                      ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
 357
 358         /* Disable NOC timeout */
 359         writel(0, &sysmgr_regs->noc_timeout);
 360
 361         return 0;
 362 }