1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
8 #include <asm/armv8/mmu.h>
9 #include <asm/global_data.h>
11 DECLARE_GLOBAL_DATA_PTR;
13 static struct mm_region socfpga_stratix10_mem_map[] = {
19 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
20 PTE_BLOCK_INNER_SHARE,
26 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
34 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
38 /* OCRAM 1MB but available 256KB */
42 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
43 PTE_BLOCK_INNER_SHARE,
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
54 .virt = 0x0100000000UL,
55 .phys = 0x0100000000UL,
56 .size = 0x1F00000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
58 PTE_BLOCK_INNER_SHARE,
61 .virt = 0x2000000000UL,
62 .phys = 0x2000000000UL,
63 .size = 0x0100000000UL,
64 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
72 struct mm_region *mem_map = socfpga_stratix10_mem_map;