arch/arm/mach-socfpga/misc_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <linux/libfdt.h>
  11 #include <altera.h>
  12 #include <miiphy.h>
  13 #include <netdev.h>
  14 #include <watchdog.h>
  15 #include <asm/arch/misc.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/sdram.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 #include <dt-bindings/reset/altr,rst-mgr.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct nic301_registers *nic301_regs =
  33         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  34 static struct scu_registers *scu_regs =
  35         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  36
  37 /*
  38  * DesignWare Ethernet initialization
  39  */
  40 #ifdef CONFIG_ETH_DESIGNWARE
  41 static void gen5_dwmac_reset(const u8 of_reset_id, const u8 phymode)
  42 {
  43         u32 physhift, reset;
  44
  45         if (of_reset_id == EMAC0_RESET) {
  46                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  47                 reset = SOCFPGA_RESET(EMAC0);
  48         } else if (of_reset_id == EMAC1_RESET) {
  49                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  50                 reset = SOCFPGA_RESET(EMAC1);
  51         } else {
  52                 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  53                 return;
  54         }
  55
  56         /* configure to PHY interface select choosed */
  57         clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
  58                         SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
  59                         phymode << physhift);
  60
  61         /* Release the EMAC controller from reset */
  62         socfpga_per_reset(reset, 0);
  63 }
  64
  65 static int socfpga_eth_reset(void)
  66 {
  67         /* Put all GMACs into RESET state. */
  68         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
  69         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
  70         return socfpga_eth_reset_common(gen5_dwmac_reset);
  71 };
  72 #else
  73 static int socfpga_eth_reset(void)
  74 {
  75         return 0;
  76 };
  77 #endif
  78
  79 static const struct {
  80         const u16       pn;
  81         const char      *name;
  82         const char      *var;
  83 } socfpga_fpga_model[] = {
  84         /* Cyclone V E */
  85         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
  86         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
  87         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
  88         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
  89         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
  90         /* Cyclone V GX/GT */
  91         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
  92         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
  93         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
  94         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
  95         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
  96         /* Cyclone V SE/SX/ST */
  97         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
  98         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
  99         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
 100         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 101         /* Arria V */
 102         { 0x2d03, "Arria V, D5", "av_d5" },
 103 };
 104
 105 static int socfpga_fpga_id(const bool print_id)
 106 {
 107         const u32 altera_mi = 0x6e;
 108         const u32 id = scan_mgr_get_fpga_id();
 109
 110         const u32 lsb = id & 0x00000001;
 111         const u32 mi = (id >> 1) & 0x000007ff;
 112         const u32 pn = (id >> 12) & 0x0000ffff;
 113         const u32 version = (id >> 28) & 0x0000000f;
 114         int i;
 115
 116         if ((mi != altera_mi) || (lsb != 1)) {
 117                 printf("FPGA:  Not Altera chip ID\n");
 118                 return -EINVAL;
 119         }
 120
 121         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 122                 if (pn == socfpga_fpga_model[i].pn)
 123                         break;
 124
 125         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 126                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 127                 return -EINVAL;
 128         }
 129
 130         if (print_id)
 131                 printf("FPGA:  Altera %s, version 0x%01x\n",
 132                        socfpga_fpga_model[i].name, version);
 133         return i;
 134 }
 135
 136 /*
 137  * Print CPU information
 138  */
 139 #if defined(CONFIG_DISPLAY_CPUINFO)
 140 int print_cpuinfo(void)
 141 {
 142         const u32 bsel =
 143                 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
 144
 145         puts("CPU:   Altera SoCFPGA Platform\n");
 146         socfpga_fpga_id(1);
 147
 148         printf("BOOT:  %s\n", bsel_str[bsel].name);
 149         return 0;
 150 }
 151 #endif
 152
 153 #ifdef CONFIG_ARCH_MISC_INIT
 154 int arch_misc_init(void)
 155 {
 156         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 157         const int fpga_id = socfpga_fpga_id(0);
 158         env_set("bootmode", bsel_str[bsel].mode);
 159         if (fpga_id >= 0)
 160                 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
 161         return socfpga_eth_reset();
 162 }
 163 #endif
 164
 165 /*
 166  * Convert all NIC-301 AMBA slaves from secure to non-secure
 167  */
 168 static void socfpga_nic301_slave_ns(void)
 169 {
 170         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 171         writel(0x1, &nic301_regs->hps2fpgaregs);
 172         writel(0x1, &nic301_regs->acp);
 173         writel(0x1, &nic301_regs->rom);
 174         writel(0x1, &nic301_regs->ocram);
 175         writel(0x1, &nic301_regs->sdrdata);
 176 }
 177
 178 void socfpga_sdram_remap_zero(void)
 179 {
 180         u32 remap;
 181
 182         socfpga_nic301_slave_ns();
 183
 184         /*
 185          * Private components security:
 186          * U-Boot : configure private timer, global timer and cpu component
 187          * access as non secure for kernel stage (as required by Linux)
 188          */
 189         setbits_le32(&scu_regs->sacr, 0xfff);
 190
 191         /* Configure the L2 controller to make SDRAM start at 0 */
 192         remap = 0x1; /* remap.mpuzero */
 193         /* Keep fpga bridge enabled when running from FPGA onchip RAM */
 194         if (socfpga_is_booting_from_fpga())
 195                 remap |= 0x8; /* remap.hps2fpga */
 196         writel(remap, &nic301_regs->remap);
 197
 198         writel(0x1, &pl310->pl310_addr_filter_start);
 199 }
 200
 201 static u32 iswgrp_handoff[8];
 202
 203 int arch_early_init_r(void)
 204 {
 205         int i;
 206
 207         /*
 208          * Write magic value into magic register to unlock support for
 209          * issuing warm reset. The ancient kernel code expects this
 210          * value to be written into the register by the bootloader, so
 211          * to support that old code, we write it here instead of in the
 212          * reset_cpu() function just before resetting the CPU.
 213          */
 214         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 215
 216         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 217                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 218
 219         socfpga_bridges_reset(1);
 220
 221         socfpga_sdram_remap_zero();
 222
 223         /* Add device descriptor to FPGA device table */
 224         socfpga_fpga_add();
 225
 226 #ifdef CONFIG_DESIGNWARE_SPI
 227         /* Get Designware SPI controller out of reset */
 228         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 229         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 230 #endif
 231
 232 #ifdef CONFIG_NAND_DENALI
 233         socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 234 #endif
 235
 236         return 0;
 237 }
 238
 239 #ifndef CONFIG_SPL_BUILD
 240 static struct socfpga_reset_manager *reset_manager_base =
 241         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
 242 static struct socfpga_sdr_ctrl *sdr_ctrl =
 243         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
 244
 245 static void socfpga_sdram_apply_static_cfg(void)
 246 {
 247         const u32 applymask = 0x8;
 248         u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
 249
 250         /*
 251          * SDRAM staticcfg register specific:
 252          * When applying the register setting, the CPU must not access
 253          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 254          * circumvent the SDRAM access issue. The idea is to make sure
 255          * that the code is in one full i-cache line by branching past
 256          * it and back. Once it is in the i-cache, we execute the core
 257          * of the code and apply the register settings.
 258          *
 259          * The code below uses 7 instructions, while the Cortex-A9 has
 260          * 32-byte cachelines, thus the limit is 8 instructions total.
 261          */
 262         asm volatile(
 263                 ".align 5                       \n"
 264                 "       b       2f              \n"
 265                 "1:     str     %0,     [%1]    \n"
 266                 "       dsb                     \n"
 267                 "       isb                     \n"
 268                 "       b       3f              \n"
 269                 "2:     b       1b              \n"
 270                 "3:     nop                     \n"
 271         : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
 272 }
 273
 274 void do_bridge_reset(int enable)
 275 {
 276         if (enable) {
 277                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 278                 socfpga_sdram_apply_static_cfg();
 279                 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
 280                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 281                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 282         } else {
 283                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 284                 writel(0, &sdr_ctrl->fpgaport_rst);
 285                 socfpga_sdram_apply_static_cfg();
 286                 writel(0, &reset_manager_base->brg_mod_reset);
 287                 writel(1, &nic301_regs->remap);
 288         }
 289 }
 290 #endif