1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
10 #include <linux/libfdt.h>
15 #include <asm/arch/misc.h>
16 #include <asm/arch/reset_manager.h>
17 #include <asm/arch/scan_manager.h>
18 #include <asm/arch/system_manager.h>
19 #include <asm/arch/nic301.h>
20 #include <asm/arch/scu.h>
21 #include <asm/pl310.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_SYS_L2_PL310
26 static const struct pl310_regs *const pl310 =
27 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
30 struct bsel bsel_str[] = {
31 { "rsvd", "Reserved", },
32 { "fpga", "FPGA (HPS2FPGA Bridge)", },
33 { "nand", "NAND Flash (1.8V)", },
34 { "nand", "NAND Flash (3.0V)", },
35 { "sd", "SD/MMC External Transceiver (1.8V)", },
36 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
37 { "qspi", "QSPI Flash (1.8V)", },
38 { "qspi", "QSPI Flash (3.0V)", },
43 if (fdtdec_setup_mem_size_base() != 0)
49 void enable_caches(void)
51 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
54 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
59 #ifdef CONFIG_SYS_L2_PL310
60 void v7_outer_cache_enable(void)
64 if (uclass_get_device(UCLASS_CACHE, 0, &dev))
65 pr_err("cache controller driver NOT found!\n");
68 void v7_outer_cache_disable(void)
70 /* Disable the L2 cache */
71 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
75 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
76 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
77 int overwrite_console(void)
84 /* add device descriptor to FPGA device table */
85 void socfpga_fpga_add(void *fpga_desc)
88 fpga_add(fpga_altera, fpga_desc);
92 int arch_cpu_init(void)
94 #ifdef CONFIG_HW_WATCHDOG
96 * In case the watchdog is enabled, make sure to (re-)configure it
97 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
98 * timeout value is still active which might too short for Linux
104 * If the HW watchdog is NOT enabled, make sure it is not running,
105 * for example because it was enabled in the preloader. This might
106 * trigger a watchdog-triggered reboot of Linux kernel later.
107 * Toggle watchdog reset, so watchdog in not running state.
109 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
110 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
116 #ifndef CONFIG_SPL_BUILD
117 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
119 unsigned int mask = ~0;
121 if (argc < 2 || argc > 3)
122 return CMD_RET_USAGE;
127 mask = simple_strtoul(argv[1], NULL, 16);
130 case 'e': /* Enable */
131 do_bridge_reset(1, mask);
133 case 'd': /* Disable */
134 do_bridge_reset(0, mask);
137 return CMD_RET_USAGE;
143 U_BOOT_CMD(bridge, 3, 1, do_bridge,
144 "SoCFPGA HPS FPGA bridge control",
145 "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
146 "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"