arch/arm/mach-socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <errno.h>
  10 #include <fdtdec.h>
  11 #include <libfdt.h>
  12 #include <altera.h>
  13 #include <miiphy.h>
  14 #include <netdev.h>
  15 #include <watchdog.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <asm/arch/scan_manager.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/dwmmc.h>
  20 #include <asm/arch/nic301.h>
  21 #include <asm/arch/scu.h>
  22 #include <asm/pl310.h>
  23
  24 #include <dt-bindings/reset/altr,rst-mgr.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 static struct pl310_regs *const pl310 =
  29         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_reset_manager *reset_manager_base =
  33         (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
  34 static struct nic301_registers *nic301_regs =
  35         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  36 static struct scu_registers *scu_regs =
  37         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  38
  39 int dram_init(void)
  40 {
  41         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  42         return 0;
  43 }
  44
  45 void enable_caches(void)
  46 {
  47 #ifndef CONFIG_SYS_ICACHE_OFF
  48         icache_enable();
  49 #endif
  50 #ifndef CONFIG_SYS_DCACHE_OFF
  51         dcache_enable();
  52 #endif
  53 }
  54
  55 void v7_outer_cache_enable(void)
  56 {
  57         /* Disable the L2 cache */
  58         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  59
  60         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  61         setbits_le32(&pl310->pl310_aux_ctrl,
  62                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  63                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  64                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  65
  66         /* Enable the L2 cache */
  67         setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  68 }
  69
  70 void v7_outer_cache_disable(void)
  71 {
  72         /* Disable the L2 cache */
  73         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  74 }
  75
  76 /*
  77  * DesignWare Ethernet initialization
  78  */
  79 #ifdef CONFIG_ETH_DESIGNWARE
  80 static void dwmac_deassert_reset(const unsigned int of_reset_id,
  81                                  const u32 phymode)
  82 {
  83         u32 physhift, reset;
  84
  85         if (of_reset_id == EMAC0_RESET) {
  86                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  87                 reset = SOCFPGA_RESET(EMAC0);
  88         } else if (of_reset_id == EMAC1_RESET) {
  89                 physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  90                 reset = SOCFPGA_RESET(EMAC1);
  91         } else {
  92                 printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
  93                 return;
  94         }
  95
  96         /* Clearing emac0 PHY interface select to 0 */
  97         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  98                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  99
 100         /* configure to PHY interface select choosed */
 101         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
 102                      phymode << physhift);
 103
 104         /* Release the EMAC controller from reset */
 105         socfpga_per_reset(reset, 0);
 106 }
 107
 108 static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
 109 {
 110         if (!phymode)
 111                 return -EINVAL;
 112
 113         if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
 114                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 115                 return 0;
 116         }
 117
 118         if (!strcmp(phymode, "rgmii")) {
 119                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
 120                 return 0;
 121         }
 122
 123         if (!strcmp(phymode, "rmii")) {
 124                 *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
 125                 return 0;
 126         }
 127
 128         return -EINVAL;
 129 }
 130
 131 static int socfpga_eth_reset(void)
 132 {
 133         const void *fdt = gd->fdt_blob;
 134         struct fdtdec_phandle_args args;
 135         const char *phy_mode;
 136         u32 phy_modereg;
 137         int nodes[2];   /* Max. two GMACs */
 138         int ret, count;
 139         int i, node;
 140
 141         /* Put both GMACs into RESET state. */
 142         socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
 143         socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
 144
 145         count = fdtdec_find_aliases_for_id(fdt, "ethernet",
 146                                            COMPAT_ALTERA_SOCFPGA_DWMAC,
 147                                            nodes, ARRAY_SIZE(nodes));
 148         for (i = 0; i < count; i++) {
 149                 node = nodes[i];
 150                 if (node <= 0)
 151                         continue;
 152
 153                 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
 154                                                      "#reset-cells", 1, 0,
 155                                                      &args);
 156                 if (ret || (args.args_count != 1)) {
 157                         debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
 158                         continue;
 159                 }
 160
 161                 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
 162                 ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
 163                 if (ret) {
 164                         debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
 165                         continue;
 166                 }
 167
 168                 dwmac_deassert_reset(args.args[0], phy_modereg);
 169         }
 170
 171         return 0;
 172 }
 173 #else
 174 static int socfpga_eth_reset(void)
 175 {
 176         return 0
 177 };
 178 #endif
 179
 180 struct {
 181         const char      *mode;
 182         const char      *name;
 183 } bsel_str[] = {
 184         { "rsvd", "Reserved", },
 185         { "fpga", "FPGA (HPS2FPGA Bridge)", },
 186         { "nand", "NAND Flash (1.8V)", },
 187         { "nand", "NAND Flash (3.0V)", },
 188         { "sd", "SD/MMC External Transceiver (1.8V)", },
 189         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
 190         { "qspi", "QSPI Flash (1.8V)", },
 191         { "qspi", "QSPI Flash (3.0V)", },
 192 };
 193
 194 static const struct {
 195         const u16       pn;
 196         const char      *name;
 197         const char      *var;
 198 } const socfpga_fpga_model[] = {
 199         /* Cyclone V E */
 200         { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
 201         { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
 202         { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
 203         { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
 204         { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
 205         /* Cyclone V GX/GT */
 206         { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
 207         { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
 208         { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
 209         { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
 210         { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
 211         /* Cyclone V SE/SX/ST */
 212         { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
 213         { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
 214         { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
 215         { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
 216         /* Arria V */
 217         { 0x2d03, "Arria V, D5", "av_d5" },
 218 };
 219
 220 static int socfpga_fpga_id(const bool print_id)
 221 {
 222         const u32 altera_mi = 0x6e;
 223         const u32 id = scan_mgr_get_fpga_id();
 224
 225         const u32 lsb = id & 0x00000001;
 226         const u32 mi = (id >> 1) & 0x000007ff;
 227         const u32 pn = (id >> 12) & 0x0000ffff;
 228         const u32 version = (id >> 28) & 0x0000000f;
 229         int i;
 230
 231         if ((mi != altera_mi) || (lsb != 1)) {
 232                 printf("FPGA:  Not Altera chip ID\n");
 233                 return -EINVAL;
 234         }
 235
 236         for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
 237                 if (pn == socfpga_fpga_model[i].pn)
 238                         break;
 239
 240         if (i == ARRAY_SIZE(socfpga_fpga_model)) {
 241                 printf("FPGA:  Unknown Altera chip, ID 0x%08x\n", id);
 242                 return -EINVAL;
 243         }
 244
 245         if (print_id)
 246                 printf("FPGA:  Altera %s, version 0x%01x\n",
 247                        socfpga_fpga_model[i].name, version);
 248         return i;
 249 }
 250
 251 /*
 252  * Print CPU information
 253  */
 254 #if defined(CONFIG_DISPLAY_CPUINFO)
 255 int print_cpuinfo(void)
 256 {
 257         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 258         puts("CPU:   Altera SoCFPGA Platform\n");
 259         socfpga_fpga_id(1);
 260         printf("BOOT:  %s\n", bsel_str[bsel].name);
 261         return 0;
 262 }
 263 #endif
 264
 265 #ifdef CONFIG_ARCH_MISC_INIT
 266 int arch_misc_init(void)
 267 {
 268         const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 269         const int fpga_id = socfpga_fpga_id(0);
 270         setenv("bootmode", bsel_str[bsel].mode);
 271         if (fpga_id >= 0)
 272                 setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
 273         return socfpga_eth_reset();
 274 }
 275 #endif
 276
 277 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 278 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 279 int overwrite_console(void)
 280 {
 281         return 0;
 282 }
 283 #endif
 284
 285 #ifdef CONFIG_FPGA
 286 /*
 287  * FPGA programming support for SoC FPGA Cyclone V
 288  */
 289 static Altera_desc altera_fpga[] = {
 290         {
 291                 /* Family */
 292                 Altera_SoCFPGA,
 293                 /* Interface type */
 294                 fast_passive_parallel,
 295                 /* No limitation as additional data will be ignored */
 296                 -1,
 297                 /* No device function table */
 298                 NULL,
 299                 /* Base interface address specified in driver */
 300                 NULL,
 301                 /* No cookie implementation */
 302                 0
 303         },
 304 };
 305
 306 /* add device descriptor to FPGA device table */
 307 static void socfpga_fpga_add(void)
 308 {
 309         int i;
 310         fpga_init();
 311         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 312                 fpga_add(fpga_altera, &altera_fpga[i]);
 313 }
 314 #else
 315 static inline void socfpga_fpga_add(void) {}
 316 #endif
 317
 318 int arch_cpu_init(void)
 319 {
 320 #ifdef CONFIG_HW_WATCHDOG
 321         /*
 322          * In case the watchdog is enabled, make sure to (re-)configure it
 323          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 324          * timeout value is still active which might too short for Linux
 325          * booting.
 326          */
 327         hw_watchdog_init();
 328 #else
 329         /*
 330          * If the HW watchdog is NOT enabled, make sure it is not running,
 331          * for example because it was enabled in the preloader. This might
 332          * trigger a watchdog-triggered reboot of Linux kernel later.
 333          * Toggle watchdog reset, so watchdog in not running state.
 334          */
 335         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 336         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 337 #endif
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * Convert all NIC-301 AMBA slaves from secure to non-secure
 344  */
 345 static void socfpga_nic301_slave_ns(void)
 346 {
 347         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 348         writel(0x1, &nic301_regs->hps2fpgaregs);
 349         writel(0x1, &nic301_regs->acp);
 350         writel(0x1, &nic301_regs->rom);
 351         writel(0x1, &nic301_regs->ocram);
 352         writel(0x1, &nic301_regs->sdrdata);
 353 }
 354
 355 static uint32_t iswgrp_handoff[8];
 356
 357 int arch_early_init_r(void)
 358 {
 359         int i;
 360
 361         /*
 362          * Write magic value into magic register to unlock support for
 363          * issuing warm reset. The ancient kernel code expects this
 364          * value to be written into the register by the bootloader, so
 365          * to support that old code, we write it here instead of in the
 366          * reset_cpu() function just before reseting the CPU.
 367          */
 368         writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
 369
 370         for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
 371                 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
 372
 373         socfpga_bridges_reset(1);
 374         socfpga_nic301_slave_ns();
 375
 376         /*
 377          * Private components security:
 378          * U-Boot : configure private timer, global timer and cpu component
 379          * access as non secure for kernel stage (as required by Linux)
 380          */
 381         setbits_le32(&scu_regs->sacr, 0xfff);
 382
 383         /* Configure the L2 controller to make SDRAM start at 0 */
 384 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 385         writel(0x2, &nic301_regs->remap);
 386 #else
 387         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 388         writel(0x1, &pl310->pl310_addr_filter_start);
 389 #endif
 390
 391         /* Add device descriptor to FPGA device table */
 392         socfpga_fpga_add();
 393
 394 #ifdef CONFIG_DESIGNWARE_SPI
 395         /* Get Designware SPI controller out of reset */
 396         socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
 397         socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
 398 #endif
 399
 400 #ifdef CONFIG_NAND_DENALI
 401         socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
 402 #endif
 403
 404         return 0;
 405 }
 406
 407 static void socfpga_sdram_apply_static_cfg(void)
 408 {
 409         const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
 410         const uint32_t applymask = 0x8;
 411         uint32_t val = readl(staticcfg) | applymask;
 412
 413         /*
 414          * SDRAM staticcfg register specific:
 415          * When applying the register setting, the CPU must not access
 416          * SDRAM. Luckily for us, we can abuse i-cache here to help us
 417          * circumvent the SDRAM access issue. The idea is to make sure
 418          * that the code is in one full i-cache line by branching past
 419          * it and back. Once it is in the i-cache, we execute the core
 420          * of the code and apply the register settings.
 421          *
 422          * The code below uses 7 instructions, while the Cortex-A9 has
 423          * 32-byte cachelines, thus the limit is 8 instructions total.
 424          */
 425         asm volatile(
 426                 ".align 5                       \n"
 427                 "       b       2f              \n"
 428                 "1:     str     %0,     [%1]    \n"
 429                 "       dsb                     \n"
 430                 "       isb                     \n"
 431                 "       b       3f              \n"
 432                 "2:     b       1b              \n"
 433                 "3:     nop                     \n"
 434         : : "r"(val), "r"(staticcfg) : "memory", "cc");
 435 }
 436
 437 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 438 {
 439         if (argc != 2)
 440                 return CMD_RET_USAGE;
 441
 442         argv++;
 443
 444         switch (*argv[0]) {
 445         case 'e':       /* Enable */
 446                 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
 447                 socfpga_sdram_apply_static_cfg();
 448                 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
 449                 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
 450                 writel(iswgrp_handoff[1], &nic301_regs->remap);
 451                 break;
 452         case 'd':       /* Disable */
 453                 writel(0, &sysmgr_regs->fpgaintfgrp_module);
 454                 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
 455                 socfpga_sdram_apply_static_cfg();
 456                 writel(0, &reset_manager_base->brg_mod_reset);
 457                 writel(1, &nic301_regs->remap);
 458                 break;
 459         default:
 460                 return CMD_RET_USAGE;
 461         }
 462
 463         return 0;
 464 }
 465
 466 U_BOOT_CMD(
 467         bridge, 2, 1, do_bridge,
 468         "SoCFPGA HPS FPGA bridge control",
 469         "enable  - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 470         "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 471         ""
 472 );