arch/arm/mach-socfpga/misc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <hang.h>
   9 #include <asm/cache.h>
  10 #include <init.h>
  11 #include <asm/io.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <linux/libfdt.h>
  15 #include <altera.h>
  16 #include <miiphy.h>
  17 #include <netdev.h>
  18 #include <watchdog.h>
  19 #include <asm/arch/misc.h>
  20 #include <asm/arch/reset_manager.h>
  21 #include <asm/arch/scan_manager.h>
  22 #include <asm/arch/system_manager.h>
  23 #include <asm/arch/nic301.h>
  24 #include <asm/arch/scu.h>
  25 #include <asm/pl310.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 phys_addr_t socfpga_clkmgr_base __section(".data");
  30 phys_addr_t socfpga_rstmgr_base __section(".data");
  31 phys_addr_t socfpga_sysmgr_base __section(".data");
  32
  33 #ifdef CONFIG_SYS_L2_PL310
  34 static const struct pl310_regs *const pl310 =
  35         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  36 #endif
  37
  38 struct bsel bsel_str[] = {
  39         { "rsvd", "Reserved", },
  40         { "fpga", "FPGA (HPS2FPGA Bridge)", },
  41         { "nand", "NAND Flash (1.8V)", },
  42         { "nand", "NAND Flash (3.0V)", },
  43         { "sd", "SD/MMC External Transceiver (1.8V)", },
  44         { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  45         { "qspi", "QSPI Flash (1.8V)", },
  46         { "qspi", "QSPI Flash (3.0V)", },
  47 };
  48
  49 int dram_init(void)
  50 {
  51         if (fdtdec_setup_mem_size_base() != 0)
  52                 return -EINVAL;
  53
  54         return 0;
  55 }
  56
  57 void enable_caches(void)
  58 {
  59 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  60         icache_enable();
  61 #endif
  62 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  63         dcache_enable();
  64 #endif
  65 }
  66
  67 #ifdef CONFIG_SYS_L2_PL310
  68 void v7_outer_cache_enable(void)
  69 {
  70         struct udevice *dev;
  71
  72         if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  73                 pr_err("cache controller driver NOT found!\n");
  74 }
  75
  76 void v7_outer_cache_disable(void)
  77 {
  78         /* Disable the L2 cache */
  79         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  80 }
  81
  82 void socfpga_pl310_clear(void)
  83 {
  84         u32 mask = 0xff, ena = 0;
  85
  86         icache_enable();
  87
  88         /* Disable the L2 cache */
  89         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  90
  91         writel(0x0, &pl310->pl310_tag_latency_ctrl);
  92         writel(0x10, &pl310->pl310_data_latency_ctrl);
  93
  94         /* enable BRESP, instruction and data prefetch, full line of zeroes */
  95         setbits_le32(&pl310->pl310_aux_ctrl,
  96                      L310_AUX_CTRL_DATA_PREFETCH_MASK |
  97                      L310_AUX_CTRL_INST_PREFETCH_MASK |
  98                      L310_SHARED_ATT_OVERRIDE_ENABLE);
  99
 100         /* Enable the L2 cache */
 101         ena = readl(&pl310->pl310_ctrl);
 102         ena |= L2X0_CTRL_EN;
 103
 104         /*
 105          * Invalidate the PL310 L2 cache. Keep the invalidation code
 106          * entirely in L1 I-cache to avoid any bus traffic through
 107          * the L2.
 108          */
 109         asm volatile(
 110                 ".align 5                       \n"
 111                 "       b       3f              \n"
 112                 "1:     str     %1,     [%4]    \n"
 113                 "       dsb                     \n"
 114                 "       isb                     \n"
 115                 "       str     %0,     [%2]    \n"
 116                 "       dsb                     \n"
 117                 "       isb                     \n"
 118                 "2:     ldr     %0,     [%2]    \n"
 119                 "       cmp     %0,     #0      \n"
 120                 "       bne     2b              \n"
 121                 "       str     %0,     [%3]    \n"
 122                 "       dsb                     \n"
 123                 "       isb                     \n"
 124                 "       b       4f              \n"
 125                 "3:     b       1b              \n"
 126                 "4:     nop                     \n"
 127         : "+r"(mask), "+r"(ena)
 128         : "r"(&pl310->pl310_inv_way),
 129           "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
 130         : "memory", "cc");
 131
 132         /* Disable the L2 cache */
 133         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 134 }
 135 #endif
 136
 137 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 138 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 139 int overwrite_console(void)
 140 {
 141         return 0;
 142 }
 143 #endif
 144
 145 #ifdef CONFIG_FPGA
 146 /* add device descriptor to FPGA device table */
 147 void socfpga_fpga_add(void *fpga_desc)
 148 {
 149         fpga_init();
 150         fpga_add(fpga_altera, fpga_desc);
 151 }
 152 #endif
 153
 154 int arch_cpu_init(void)
 155 {
 156         socfpga_get_managers_addr();
 157
 158 #ifdef CONFIG_HW_WATCHDOG
 159         /*
 160          * In case the watchdog is enabled, make sure to (re-)configure it
 161          * so that the defined timeout is valid. Otherwise the SPL (Perloader)
 162          * timeout value is still active which might too short for Linux
 163          * booting.
 164          */
 165         hw_watchdog_init();
 166 #else
 167         /*
 168          * If the HW watchdog is NOT enabled, make sure it is not running,
 169          * for example because it was enabled in the preloader. This might
 170          * trigger a watchdog-triggered reboot of Linux kernel later.
 171          * Toggle watchdog reset, so watchdog in not running state.
 172          */
 173         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 174         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 175 #endif
 176
 177         return 0;
 178 }
 179
 180 #ifndef CONFIG_SPL_BUILD
 181 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 182 {
 183         unsigned int mask = ~0;
 184
 185         if (argc < 2 || argc > 3)
 186                 return CMD_RET_USAGE;
 187
 188         argv++;
 189
 190         if (argc == 3)
 191                 mask = simple_strtoul(argv[1], NULL, 16);
 192
 193         switch (*argv[0]) {
 194         case 'e':       /* Enable */
 195                 do_bridge_reset(1, mask);
 196                 break;
 197         case 'd':       /* Disable */
 198                 do_bridge_reset(0, mask);
 199                 break;
 200         default:
 201                 return CMD_RET_USAGE;
 202         }
 203
 204         return 0;
 205 }
 206
 207 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 208            "SoCFPGA HPS FPGA bridge control",
 209            "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 210            "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
 211            ""
 212 );
 213
 214 #endif
 215
 216 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
 217 {
 218         const void *blob = gd->fdt_blob;
 219         struct fdt_resource r;
 220         int node;
 221         int ret;
 222
 223         node = fdt_node_offset_by_compatible(blob, -1, compat);
 224         if (node < 0)
 225                 return node;
 226
 227         if (!fdtdec_get_is_enabled(blob, node))
 228                 return -ENODEV;
 229
 230         ret = fdt_get_resource(blob, node, "reg", 0, &r);
 231         if (ret)
 232                 return ret;
 233
 234         *base = (phys_addr_t)r.start;
 235
 236         return 0;
 237 }
 238
 239 void socfpga_get_managers_addr(void)
 240 {
 241         int ret;
 242
 243         ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
 244         if (ret)
 245                 hang();
 246
 247         ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
 248         if (ret)
 249                 hang();
 250
 251 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 252         ret = socfpga_get_base_addr("intel,agilex-clkmgr",
 253                                     &socfpga_clkmgr_base);
 254 #else
 255         ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
 256 #endif
 257         if (ret)
 258                 hang();
 259 }
 260
 261 phys_addr_t socfpga_get_rstmgr_addr(void)
 262 {
 263         return socfpga_rstmgr_base;
 264 }
 265
 266 phys_addr_t socfpga_get_sysmgr_addr(void)
 267 {
 268         return socfpga_sysmgr_base;
 269 }
 270
 271 phys_addr_t socfpga_get_clkmgr_addr(void)
 272 {
 273         return socfpga_clkmgr_base;
 274 }