1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
12 #include <linux/libfdt.h>
17 #include <asm/arch/misc.h>
18 #include <asm/arch/reset_manager.h>
19 #include <asm/arch/scan_manager.h>
20 #include <asm/arch/system_manager.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/arch/scu.h>
23 #include <asm/pl310.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 phys_addr_t socfpga_clkmgr_base __section(".data");
28 phys_addr_t socfpga_rstmgr_base __section(".data");
29 phys_addr_t socfpga_sysmgr_base __section(".data");
31 #ifdef CONFIG_SYS_L2_PL310
32 static const struct pl310_regs *const pl310 =
33 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
36 struct bsel bsel_str[] = {
37 { "rsvd", "Reserved", },
38 { "fpga", "FPGA (HPS2FPGA Bridge)", },
39 { "nand", "NAND Flash (1.8V)", },
40 { "nand", "NAND Flash (3.0V)", },
41 { "sd", "SD/MMC External Transceiver (1.8V)", },
42 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
43 { "qspi", "QSPI Flash (1.8V)", },
44 { "qspi", "QSPI Flash (3.0V)", },
49 if (fdtdec_setup_mem_size_base() != 0)
55 void enable_caches(void)
57 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
60 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
65 #ifdef CONFIG_SYS_L2_PL310
66 void v7_outer_cache_enable(void)
70 if (uclass_get_device(UCLASS_CACHE, 0, &dev))
71 pr_err("cache controller driver NOT found!\n");
74 void v7_outer_cache_disable(void)
76 /* Disable the L2 cache */
77 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
80 void socfpga_pl310_clear(void)
82 u32 mask = 0xff, ena = 0;
86 /* Disable the L2 cache */
87 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
89 writel(0x0, &pl310->pl310_tag_latency_ctrl);
90 writel(0x10, &pl310->pl310_data_latency_ctrl);
92 /* enable BRESP, instruction and data prefetch, full line of zeroes */
93 setbits_le32(&pl310->pl310_aux_ctrl,
94 L310_AUX_CTRL_DATA_PREFETCH_MASK |
95 L310_AUX_CTRL_INST_PREFETCH_MASK |
96 L310_SHARED_ATT_OVERRIDE_ENABLE);
98 /* Enable the L2 cache */
99 ena = readl(&pl310->pl310_ctrl);
103 * Invalidate the PL310 L2 cache. Keep the invalidation code
104 * entirely in L1 I-cache to avoid any bus traffic through
125 : "+r"(mask), "+r"(ena)
126 : "r"(&pl310->pl310_inv_way),
127 "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
130 /* Disable the L2 cache */
131 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
135 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
136 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
137 int overwrite_console(void)
144 /* add device descriptor to FPGA device table */
145 void socfpga_fpga_add(void *fpga_desc)
148 fpga_add(fpga_altera, fpga_desc);
152 int arch_cpu_init(void)
154 socfpga_get_managers_addr();
156 #ifdef CONFIG_HW_WATCHDOG
158 * In case the watchdog is enabled, make sure to (re-)configure it
159 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
160 * timeout value is still active which might too short for Linux
166 * If the HW watchdog is NOT enabled, make sure it is not running,
167 * for example because it was enabled in the preloader. This might
168 * trigger a watchdog-triggered reboot of Linux kernel later.
169 * Toggle watchdog reset, so watchdog in not running state.
171 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
172 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
178 #ifndef CONFIG_SPL_BUILD
179 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
181 unsigned int mask = ~0;
183 if (argc < 2 || argc > 3)
184 return CMD_RET_USAGE;
189 mask = simple_strtoul(argv[1], NULL, 16);
192 case 'e': /* Enable */
193 do_bridge_reset(1, mask);
195 case 'd': /* Disable */
196 do_bridge_reset(0, mask);
199 return CMD_RET_USAGE;
205 U_BOOT_CMD(bridge, 3, 1, do_bridge,
206 "SoCFPGA HPS FPGA bridge control",
207 "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
208 "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
214 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
216 const void *blob = gd->fdt_blob;
217 struct fdt_resource r;
221 node = fdt_node_offset_by_compatible(blob, -1, compat);
225 if (!fdtdec_get_is_enabled(blob, node))
228 ret = fdt_get_resource(blob, node, "reg", 0, &r);
232 *base = (phys_addr_t)r.start;
237 void socfpga_get_managers_addr(void)
241 ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
245 ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
249 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
250 ret = socfpga_get_base_addr("intel,agilex-clkmgr",
251 &socfpga_clkmgr_base);
253 ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
259 phys_addr_t socfpga_get_rstmgr_addr(void)
261 return socfpga_rstmgr_base;
264 phys_addr_t socfpga_get_sysmgr_addr(void)
266 return socfpga_sysmgr_base;
269 phys_addr_t socfpga_get_clkmgr_addr(void)
271 return socfpga_clkmgr_base;