1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
13 #include <linux/libfdt.h>
18 #include <asm/arch/misc.h>
19 #include <asm/arch/reset_manager.h>
20 #include <asm/arch/scan_manager.h>
21 #include <asm/arch/system_manager.h>
22 #include <asm/arch/nic301.h>
23 #include <asm/arch/scu.h>
24 #include <asm/pl310.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 phys_addr_t socfpga_clkmgr_base __section(".data");
29 phys_addr_t socfpga_rstmgr_base __section(".data");
30 phys_addr_t socfpga_sysmgr_base __section(".data");
32 #ifdef CONFIG_SYS_L2_PL310
33 static const struct pl310_regs *const pl310 =
34 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
37 struct bsel bsel_str[] = {
38 { "rsvd", "Reserved", },
39 { "fpga", "FPGA (HPS2FPGA Bridge)", },
40 { "nand", "NAND Flash (1.8V)", },
41 { "nand", "NAND Flash (3.0V)", },
42 { "sd", "SD/MMC External Transceiver (1.8V)", },
43 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
44 { "qspi", "QSPI Flash (1.8V)", },
45 { "qspi", "QSPI Flash (3.0V)", },
50 if (fdtdec_setup_mem_size_base() != 0)
56 void enable_caches(void)
58 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
61 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
66 #ifdef CONFIG_SYS_L2_PL310
67 void v7_outer_cache_enable(void)
71 if (uclass_get_device(UCLASS_CACHE, 0, &dev))
72 pr_err("cache controller driver NOT found!\n");
75 void v7_outer_cache_disable(void)
77 /* Disable the L2 cache */
78 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
81 void socfpga_pl310_clear(void)
83 u32 mask = 0xff, ena = 0;
87 /* Disable the L2 cache */
88 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
90 writel(0x0, &pl310->pl310_tag_latency_ctrl);
91 writel(0x10, &pl310->pl310_data_latency_ctrl);
93 /* enable BRESP, instruction and data prefetch, full line of zeroes */
94 setbits_le32(&pl310->pl310_aux_ctrl,
95 L310_AUX_CTRL_DATA_PREFETCH_MASK |
96 L310_AUX_CTRL_INST_PREFETCH_MASK |
97 L310_SHARED_ATT_OVERRIDE_ENABLE);
99 /* Enable the L2 cache */
100 ena = readl(&pl310->pl310_ctrl);
104 * Invalidate the PL310 L2 cache. Keep the invalidation code
105 * entirely in L1 I-cache to avoid any bus traffic through
126 : "+r"(mask), "+r"(ena)
127 : "r"(&pl310->pl310_inv_way),
128 "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
131 /* Disable the L2 cache */
132 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
136 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
137 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
138 int overwrite_console(void)
145 /* add device descriptor to FPGA device table */
146 void socfpga_fpga_add(void *fpga_desc)
149 fpga_add(fpga_altera, fpga_desc);
153 int arch_cpu_init(void)
155 socfpga_get_managers_addr();
157 #ifdef CONFIG_HW_WATCHDOG
159 * In case the watchdog is enabled, make sure to (re-)configure it
160 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
161 * timeout value is still active which might too short for Linux
167 * If the HW watchdog is NOT enabled, make sure it is not running,
168 * for example because it was enabled in the preloader. This might
169 * trigger a watchdog-triggered reboot of Linux kernel later.
170 * Toggle watchdog reset, so watchdog in not running state.
172 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
173 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
179 #ifndef CONFIG_SPL_BUILD
180 static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
182 unsigned int mask = ~0;
184 if (argc < 2 || argc > 3)
185 return CMD_RET_USAGE;
190 mask = simple_strtoul(argv[1], NULL, 16);
193 case 'e': /* Enable */
194 do_bridge_reset(1, mask);
196 case 'd': /* Disable */
197 do_bridge_reset(0, mask);
200 return CMD_RET_USAGE;
206 U_BOOT_CMD(bridge, 3, 1, do_bridge,
207 "SoCFPGA HPS FPGA bridge control",
208 "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
209 "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
215 static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
217 const void *blob = gd->fdt_blob;
218 struct fdt_resource r;
222 node = fdt_node_offset_by_compatible(blob, -1, compat);
226 if (!fdtdec_get_is_enabled(blob, node))
229 ret = fdt_get_resource(blob, node, "reg", 0, &r);
233 *base = (phys_addr_t)r.start;
238 void socfpga_get_managers_addr(void)
242 ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
246 ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
250 #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
251 ret = socfpga_get_base_addr("intel,agilex-clkmgr",
252 &socfpga_clkmgr_base);
254 ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
260 phys_addr_t socfpga_get_rstmgr_addr(void)
262 return socfpga_rstmgr_base;
265 phys_addr_t socfpga_get_sysmgr_addr(void)
267 return socfpga_sysmgr_base;
270 phys_addr_t socfpga_get_clkmgr_addr(void)
272 return socfpga_clkmgr_base;