1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
11 #include <asm/arch/mailbox_s10.h>
12 #include <asm/arch/system_manager.h>
13 #include <asm/secure.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define MBOX_READL(reg) \
18 readl(SOCFPGA_MAILBOX_ADDRESS + (reg))
20 #define MBOX_WRITEL(data, reg) \
21 writel(data, SOCFPGA_MAILBOX_ADDRESS + (reg))
23 #define MBOX_READ_RESP_BUF(rout) \
24 MBOX_READL(MBOX_RESP_BUF + ((rout) * sizeof(u32)))
26 #define MBOX_WRITE_CMD_BUF(data, cin) \
27 MBOX_WRITEL(data, MBOX_CMD_BUF + ((cin) * sizeof(u32)))
29 static __always_inline int mbox_polling_resp(u32 rout)
32 unsigned long i = 2000;
35 rin = MBOX_READL(MBOX_RIN);
46 /* Check for available slot and write to circular buffer.
47 * It also update command valid offset (cin) register.
49 static __always_inline int mbox_fill_cmd_circular_buff(u32 header, u32 len,
56 cin = MBOX_READL(MBOX_CIN) % MBOX_CMD_BUFFER_SIZE;
57 cout = MBOX_READL(MBOX_COUT) % MBOX_CMD_BUFFER_SIZE;
59 /* if command buffer is full or not enough free space
60 * to fit the data. Note, len is in u32 unit.
62 if (((cin + 1) % MBOX_CMD_BUFFER_SIZE) == cout ||
63 ((MBOX_CMD_BUFFER_SIZE - cin + cout - 1) %
64 MBOX_CMD_BUFFER_SIZE) < (len + 1))
67 /* write header to circular buffer */
68 MBOX_WRITE_CMD_BUF(header, cin++);
69 /* wrapping around when it reach the buffer size */
70 cin %= MBOX_CMD_BUFFER_SIZE;
73 for (i = 0; i < len; i++) {
74 MBOX_WRITE_CMD_BUF(arg[i], cin++);
75 /* wrapping around when it reach the buffer size */
76 cin %= MBOX_CMD_BUFFER_SIZE;
79 /* write command valid offset */
80 MBOX_WRITEL(cin, MBOX_CIN);
85 /* Check the command and fill it into circular buffer */
86 static __always_inline int mbox_prepare_cmd_only(u8 id, u32 cmd,
87 u8 is_indirect, u32 len,
93 /* Total length is command + argument length */
94 if ((len + 1) > MBOX_CMD_BUFFER_SIZE)
97 if (cmd > MBOX_MAX_CMD_INDEX)
100 header = MBOX_CMD_HEADER(MBOX_CLIENT_ID_UBOOT, id, len,
101 (is_indirect) ? 1 : 0, cmd);
103 ret = mbox_fill_cmd_circular_buff(header, len, arg);
108 /* Send command only without waiting for responses from SDM */
109 static __always_inline int mbox_send_cmd_only_common(u8 id, u32 cmd,
110 u8 is_indirect, u32 len,
113 int ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
115 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
120 /* Return number of responses received in buffer */
121 static __always_inline int __mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
127 /* clear doorbell from SDM if it was SET */
128 if (MBOX_READL(MBOX_DOORBELL_FROM_SDM) & 1)
129 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
131 /* read current response offset */
132 rout = MBOX_READL(MBOX_ROUT);
133 /* read response valid offset */
134 rin = MBOX_READL(MBOX_RIN);
136 while (rin != rout && (resp_len < resp_buf_max_len)) {
137 /* Response received */
139 resp_buf[resp_len++] = MBOX_READ_RESP_BUF(rout);
142 /* wrapping around when it reach the buffer size */
143 rout %= MBOX_RESP_BUFFER_SIZE;
144 /* update next ROUT */
145 MBOX_WRITEL(rout, MBOX_ROUT);
151 /* Support one command and up to 31 words argument length only */
152 static __always_inline int mbox_send_cmd_common(u8 id, u32 cmd, u8 is_indirect,
153 u32 len, u32 *arg, u8 urgent,
166 /* Read status because it is toggled */
167 status = MBOX_READL(MBOX_STATUS) & MBOX_STATUS_UA_MSK;
168 /* Write urgent command to urgent register */
169 MBOX_WRITEL(cmd, MBOX_URG);
171 ret = mbox_prepare_cmd_only(id, cmd, is_indirect, len, arg);
177 MBOX_WRITEL(1, MBOX_DOORBELL_TO_SDM);
182 /* Wait for doorbell from SDM */
184 if (MBOX_READL(MBOX_DOORBELL_FROM_SDM))
192 /* clear interrupt */
193 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
196 u32 new_status = MBOX_READL(MBOX_STATUS);
198 /* Urgent ACK is toggled */
199 if ((new_status & MBOX_STATUS_UA_MSK) ^ status)
205 /* read current response offset */
206 rout = MBOX_READL(MBOX_ROUT);
208 /* read response valid offset */
209 rin = MBOX_READL(MBOX_RIN);
212 /* Response received */
213 resp = MBOX_READ_RESP_BUF(rout);
215 /* wrapping around when it reach the buffer size */
216 rout %= MBOX_RESP_BUFFER_SIZE;
217 /* update next ROUT */
218 MBOX_WRITEL(rout, MBOX_ROUT);
220 /* check client ID and ID */
221 if ((MBOX_RESP_CLIENT_GET(resp) ==
222 MBOX_CLIENT_ID_UBOOT) &&
223 (MBOX_RESP_ID_GET(resp) == id)) {
224 ret = MBOX_RESP_ERR_GET(resp);
229 buf_len = *resp_buf_len;
235 resp_len = MBOX_RESP_LEN_GET(resp);
237 ret = mbox_polling_resp(rout);
240 /* we need to process response buffer
241 * even caller doesn't need it
243 resp = MBOX_READ_RESP_BUF(rout);
246 rout %= MBOX_RESP_BUFFER_SIZE;
247 MBOX_WRITEL(rout, MBOX_ROUT);
249 /* copy response to buffer */
250 resp_buf[*resp_buf_len] = resp;
267 /* enable mailbox interrupts */
268 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
270 /* Ensure urgent request is cleared */
271 MBOX_WRITEL(0, MBOX_URG);
273 /* Ensure the Doorbell Interrupt is cleared */
274 MBOX_WRITEL(0, MBOX_DOORBELL_FROM_SDM);
276 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RESTART, MBOX_CMD_DIRECT, 0,
281 /* Renable mailbox interrupts after MBOX_RESTART */
282 MBOX_WRITEL(MBOX_ALL_INTRS, MBOX_FLAGS);
287 #ifdef CONFIG_CADENCE_QSPI
288 int mbox_qspi_close(void)
290 return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_CLOSE, MBOX_CMD_DIRECT,
291 0, NULL, 0, 0, NULL);
294 int mbox_qspi_open(void)
300 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN, MBOX_CMD_DIRECT,
301 0, NULL, 0, 0, NULL);
303 /* retry again by closing and reopen the QSPI again */
304 ret = mbox_qspi_close();
308 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_OPEN,
309 MBOX_CMD_DIRECT, 0, NULL, 0, 0, NULL);
314 /* HPS will directly control the QSPI controller, no longer mailbox */
316 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_QSPI_DIRECT, MBOX_CMD_DIRECT,
317 0, NULL, 0, (u32 *)&resp_buf_len,
322 /* We are getting QSPI ref clock and set into sysmgr boot register */
323 printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
325 socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
334 #endif /* CONFIG_CADENCE_QSPI */
336 int mbox_reset_cold(void)
340 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_REBOOT_HPS, MBOX_CMD_DIRECT,
341 0, NULL, 0, 0, NULL);
343 /* mailbox sent failure, wait for watchdog to kick in */
349 /* Accepted commands: CONFIG_STATUS or RECONFIG_STATUS */
350 static __always_inline int mbox_get_fpga_config_status_common(u32 cmd)
352 u32 reconfig_status_resp_len;
353 u32 reconfig_status_resp[RECONFIG_STATUS_RESPONSE_LEN];
356 reconfig_status_resp_len = RECONFIG_STATUS_RESPONSE_LEN;
357 ret = mbox_send_cmd_common(MBOX_ID_UBOOT, cmd,
358 MBOX_CMD_DIRECT, 0, NULL, 0,
359 &reconfig_status_resp_len,
360 reconfig_status_resp);
365 /* Check for any error */
366 ret = reconfig_status_resp[RECONFIG_STATUS_STATE];
367 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
370 /* Make sure nStatus is not 0 */
371 ret = reconfig_status_resp[RECONFIG_STATUS_PIN_STATUS];
372 if (!(ret & RCF_PIN_STATUS_NSTATUS))
373 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
375 ret = reconfig_status_resp[RECONFIG_STATUS_SOFTFUNC_STATUS];
376 if (ret & RCF_SOFTFUNC_STATUS_SEU_ERROR)
377 return MBOX_CFGSTAT_STATE_ERROR_HARDWARE;
379 if ((ret & RCF_SOFTFUNC_STATUS_CONF_DONE) &&
380 (ret & RCF_SOFTFUNC_STATUS_INIT_DONE) &&
381 !reconfig_status_resp[RECONFIG_STATUS_STATE])
382 return 0; /* configuration success */
384 return MBOX_CFGSTAT_STATE_CONFIG;
387 int mbox_get_fpga_config_status(u32 cmd)
389 return mbox_get_fpga_config_status_common(cmd);
392 int __secure mbox_get_fpga_config_status_psci(u32 cmd)
394 return mbox_get_fpga_config_status_common(cmd);
397 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
398 u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
400 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
401 resp_buf_len, resp_buf);
404 int __secure mbox_send_cmd_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
405 u32 *arg, u8 urgent, u32 *resp_buf_len,
408 return mbox_send_cmd_common(id, cmd, is_indirect, len, arg, urgent,
409 resp_buf_len, resp_buf);
412 int mbox_send_cmd_only(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg)
414 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
417 int __secure mbox_send_cmd_only_psci(u8 id, u32 cmd, u8 is_indirect, u32 len,
420 return mbox_send_cmd_only_common(id, cmd, is_indirect, len, arg);
423 int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len)
425 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);
428 int __secure mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len)
430 return __mbox_rcv_resp(resp_buf, resp_buf_max_len);