2 * Copyright (C) 2020 Intel Corporation. All rights reserved
4 * SPDX-License-Identifier: GPL-2.0
7 #include <asm-offsets.h>
9 #include <linux/linkage.h>
10 #include <asm/macro.h>
13 mov x29, lr /* Save LR */
15 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
16 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
18 ldr x4, =CPU_RELEASE_ADDR
20 cbz x5, slave_wait_atf
23 branch_if_slave x0, wait_for_atf
25 branch_if_slave x0, 1f
30 #if defined(CONFIG_GICV3)
32 bl gic_init_secure_percpu
33 #elif defined(CONFIG_GICV2)
36 bl gic_init_secure_percpu
40 #ifdef CONFIG_ARMV8_MULTIENTRY
41 branch_if_master x0, 2f
44 * Slave should wait for master clearing spin table.
45 * This sync prevent slaves observing incorrect
46 * value of spin table and jumping to wrong place.
48 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
52 bl gic_wait_for_interrupt
56 * All slaves will enter EL2 and optionally EL1.
58 adr x4, lowlevel_in_el2
59 ldr x5, =ES_TO_AARCH64
60 bl armv8_switch_to_el2
63 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
64 adr x4, lowlevel_in_el1
65 ldr x5, =ES_TO_AARCH64
66 bl armv8_switch_to_el1
71 #endif /* CONFIG_ARMV8_MULTIENTRY */
74 mov lr, x29 /* Restore LR */
76 ENDPROC(lowlevel_init)