1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
6 #ifndef _RESET_MANAGER_ARRIA10_H_
7 #define _RESET_MANAGER_ARRIA10_H_
9 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
11 void socfpga_watchdog_disable(void);
12 void socfpga_reset_deassert_noc_ddr_scheduler(void);
13 int socfpga_reset_deassert_bridges_handoff(void);
14 void socfpga_reset_deassert_osc1wd0(void);
15 int socfpga_bridges_reset(void);
17 #define RSTMGR_A10_STATUS 0x00
18 #define RSTMGR_A10_CTRL 0x0c
19 #define RSTMGR_A10_MPUMODRST 0x20
20 #define RSTMGR_A10_PER0MODRST 0x24
21 #define RSTMGR_A10_PER1MODRST 0x28
22 #define RSTMGR_A10_BRGMODRST 0x2c
23 #define RSTMGR_A10_SYSMODRST 0x30
25 #define RSTMGR_CTRL RSTMGR_A10_CTRL
28 * SocFPGA Arria10 reset IDs, bank mapping is as follows:
35 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
36 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
37 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
38 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
39 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
40 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
41 #define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
42 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
43 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
44 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
45 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
46 #define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
47 #define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
48 #define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
49 #define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
50 #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
51 #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
52 #define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
54 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
55 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
56 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
57 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
58 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
59 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
60 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
61 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
62 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
63 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
64 #define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
65 #define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
66 #define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
67 #define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
68 #define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
69 #define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
70 #define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
71 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
72 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
73 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
74 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
75 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
76 #define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
77 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
78 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
79 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
80 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
81 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
82 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
83 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
84 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
85 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
87 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
88 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
89 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
90 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
91 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
92 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
93 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
94 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
95 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
96 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
97 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
98 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
99 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
100 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
101 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
102 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
104 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
105 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
106 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
107 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
108 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
109 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
110 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
112 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
113 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
114 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
115 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
117 #endif /* _RESET_MANAGER_ARRIA10_H_ */