1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
7 #ifndef _CLOCK_MANAGER_S10_
8 #define _CLOCK_MANAGER_S10_
10 #include <asm/arch/clock_manager_soc64.h>
12 /* Clock speed accessors */
13 unsigned long cm_get_mpu_clk_hz(void);
14 unsigned long cm_get_sdram_clk_hz(void);
15 unsigned int cm_get_l4_sp_clk_hz(void);
16 unsigned int cm_get_mmc_controller_clk_hz(void);
17 unsigned int cm_get_qspi_controller_clk_hz(void);
18 unsigned int cm_get_spi_controller_clk_hz(void);
24 u32 main_pll_cntr2clk;
25 u32 main_pll_cntr3clk;
26 u32 main_pll_cntr4clk;
27 u32 main_pll_cntr5clk;
28 u32 main_pll_cntr6clk;
29 u32 main_pll_cntr7clk;
30 u32 main_pll_cntr8clk;
31 u32 main_pll_cntr9clk;
39 /* peripheral group */
60 void cm_basic_init(const struct cm_config * const cfg);
63 #define CLKMGR_S10_CTRL 0x00
64 #define CLKMGR_S10_STAT 0x04
65 #define CLKMGR_S10_INTRCLR 0x14
67 #define CLKMGR_S10_MAINPLL_EN 0x30
68 #define CLKMGR_S10_MAINPLL_BYPASS 0x3c
69 #define CLKMGR_S10_MAINPLL_MPUCLK 0x48
70 #define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
71 #define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
72 #define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
73 #define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
74 #define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
75 #define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
76 #define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
77 #define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
78 #define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
79 #define CLKMGR_S10_MAINPLL_NOCDIV 0x70
80 #define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
81 #define CLKMGR_S10_MAINPLL_FDBCK 0x78
82 #define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
83 #define CLKMGR_S10_MAINPLL_PLLC0 0x84
84 #define CLKMGR_S10_MAINPLL_PLLC1 0x88
85 #define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
87 #define CLKMGR_S10_PERPLL_EN 0xa4
88 #define CLKMGR_S10_PERPLL_BYPASS 0xac
89 #define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
90 #define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
91 #define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
92 #define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
93 #define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
94 #define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
95 #define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
96 #define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
97 #define CLKMGR_S10_PERPLL_EMACCTL 0xdc
98 #define CLKMGR_S10_PERPLL_GPIODIV 0xe0
99 #define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
100 #define CLKMGR_S10_PERPLL_FDBCK 0xe8
101 #define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
102 #define CLKMGR_S10_PERPLL_PLLC0 0xf4
103 #define CLKMGR_S10_PERPLL_PLLC1 0xf8
104 #define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
106 #define CLKMGR_STAT CLKMGR_S10_STAT
107 #define CLKMGR_INTER CLKMGR_S10_INTER
108 #define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
111 #define CLKMGR_CTRL_SAFEMODE BIT(0)
112 #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
113 #define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f
115 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001
116 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002
117 #define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004
118 #define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
119 #define CLKMGR_STAT_BUSY BIT(0)
120 #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
121 #define CLKMGR_STAT_PERPLL_LOCKED BIT(9)
123 #define CLKMGR_PLLGLOB_PD_MASK 0x00000001
124 #define CLKMGR_PLLGLOB_RST_MASK 0x00000002
125 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3
126 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
127 #define CLKMGR_VCO_PSRC_EOSC1 0
128 #define CLKMGR_VCO_PSRC_INTOSC 1
129 #define CLKMGR_VCO_PSRC_F2S 2
130 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f
131 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8
133 #define CLKMGR_CLKSRC_MASK 0x7
134 #define CLKMGR_CLKSRC_OFFSET 16
135 #define CLKMGR_CLKSRC_MAIN 0
136 #define CLKMGR_CLKSRC_PER 1
137 #define CLKMGR_CLKSRC_OSC1 2
138 #define CLKMGR_CLKSRC_INTOSC 3
139 #define CLKMGR_CLKSRC_FPGA 4
140 #define CLKMGR_CLKCNT_MSK 0x7ff
142 #define CLKMGR_FDBCK_MDIV_MASK 0xff
143 #define CLKMGR_FDBCK_MDIV_OFFSET 24
145 #define CLKMGR_PLLC0_DIV_MASK 0xff
146 #define CLKMGR_PLLC1_DIV_MASK 0xff
147 #define CLKMGR_PLLC0_EN_OFFSET 27
148 #define CLKMGR_PLLC1_EN_OFFSET 24
150 #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
151 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
152 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
153 #define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
154 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
155 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
157 #define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3
158 #define CLKMGR_NOCDIV_DIV1 0
159 #define CLKMGR_NOCDIV_DIV2 1
160 #define CLKMGR_NOCDIV_DIV4 2
161 #define CLKMGR_NOCDIV_DIV8 3
162 #define CLKMGR_CSPDBGCLK_DIV1 0
163 #define CLKMGR_CSPDBGCLK_DIV4 1
165 #define CLKMGR_MSCNT_CONST 200
166 #define CLKMGR_MDIV_CONST 6
167 #define CLKMGR_HSCNT_CONST 9
169 #define CLKMGR_VCOCALIB_MSCNT_MASK 0xff
170 #define CLKMGR_VCOCALIB_MSCNT_OFFSET 9
171 #define CLKMGR_VCOCALIB_HSCNT_MASK 0xff
173 #define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26
174 #define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27
175 #define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28
177 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
179 #endif /* _CLOCK_MANAGER_S10_ */