1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
6 #ifndef CLOCK_MANAGER_ARRIA10
7 #define CLOCK_MANAGER_ARRIA10
11 /* Clock manager group */
12 #define CLKMGR_A10_CTRL 0x00
13 #define CLKMGR_A10_INTR 0x04
14 #define CLKMGR_A10_STAT 0x1c
16 #define CLKMGR_A10_MAINPLL_VCO0 0x40
17 #define CLKMGR_A10_MAINPLL_VCO1 0x44
18 #define CLKMGR_A10_MAINPLL_EN 0x48
19 #define CLKMGR_A10_MAINPLL_ENS 0x4c
20 #define CLKMGR_A10_MAINPLL_ENR 0x50
21 #define CLKMGR_A10_MAINPLL_BYPASS 0x54
22 #define CLKMGR_A10_MAINPLL_BYPASSS 0x58
23 #define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
24 #define CLKMGR_A10_MAINPLL_MPUCLK 0x60
25 #define CLKMGR_A10_MAINPLL_NOCCLK 0x64
26 #define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
27 #define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
28 #define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
29 #define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
30 #define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
31 #define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
32 #define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
33 #define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
34 #define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
35 #define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
36 /* Peripheral PLL group */
37 #define CLKMGR_A10_PERPLL_VCO0 0xc0
38 #define CLKMGR_A10_PERPLL_VCO1 0xc4
39 #define CLKMGR_A10_PERPLL_EN 0xc8
40 #define CLKMGR_A10_PERPLL_ENS 0xcc
41 #define CLKMGR_A10_PERPLL_ENR 0xd0
42 #define CLKMGR_A10_PERPLL_BYPASS 0xd4
43 #define CLKMGR_A10_PERPLL_BYPASSS 0xd8
44 #define CLKMGR_A10_PERPLL_BYPASSR 0xdc
45 #define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
46 #define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
47 #define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
48 #define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
49 #define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
50 #define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
51 #define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
52 #define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
53 #define CLKMGR_A10_PERPLL_EMACCTL 0x128
54 #define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
56 #define CLKMGR_A10_ALTR_MPUCLK 0x140
57 #define CLKMGR_A10_ALTR_NOCCLK 0x144
59 #define CLKMGR_STAT CLKMGR_A10_STAT
60 #define CLKMGR_INTER CLKMGR_A10_INTER
61 #define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
63 #ifdef CONFIG_SPL_BUILD
64 int cm_basic_init(const void *blob);
67 unsigned int cm_get_l4_sp_clk_hz(void);
68 unsigned long cm_get_mpu_clk_hz(void);
70 unsigned int cm_get_qspi_controller_clk_hz(void);
72 #endif /* __ASSEMBLY__ */
74 #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
75 CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
78 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
79 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
80 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
81 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
82 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
83 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
84 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
85 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
86 #define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
87 #define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
88 #define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
89 #define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
90 #define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
93 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
94 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
95 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
96 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
97 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
98 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
99 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
100 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
101 #define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
102 #define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
103 #define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
104 #define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
105 #define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
106 #define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
107 #define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
108 #define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
109 #define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
110 #define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
111 #define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
112 #define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
113 #define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
114 #define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
115 #define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
116 #define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
117 #define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
118 #define CLKMGR_PERPLL_EN_RESET 0x00000f7f
119 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
120 #define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
121 #define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
122 #define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
123 #define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
124 #define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
125 #define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
126 #define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
127 #define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
128 #define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
129 #define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
130 #define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
131 #define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
132 #define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
133 #define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
134 #define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
135 #define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
136 #define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
137 #define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
138 #define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
139 #define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
140 #define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
141 #define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
142 #define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
144 #define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
145 #define CLKMGR_PERPLLGRP_SRC_MAIN 0
146 #define CLKMGR_PERPLLGRP_SRC_PERI 1
147 #define CLKMGR_PERPLLGRP_SRC_OSC1 2
148 #define CLKMGR_PERPLLGRP_SRC_INTOSC 3
149 #define CLKMGR_PERPLLGRP_SRC_FPGA 4
151 /* bit shifting macro */
152 #define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
153 #define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
154 #define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
155 #define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
156 #define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
157 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
158 #define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
159 #define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
160 #define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
161 #define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
162 #define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
163 #define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
164 #define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
165 #define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
166 #define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
167 #define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
168 #define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
169 #define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
170 #define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
171 #define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
172 #define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
173 #define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
174 #define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
175 #define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
176 #define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
177 #define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
179 /* PLL ramping work around */
180 #define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
181 #define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
182 #define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
183 #define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
185 #define CLKMGR_STAT_BUSY BIT(0)
187 #endif /* CLOCK_MANAGER_ARRIA10 */