1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
9 #include <asm/arch/clock_manager.h>
10 #include <asm/arch/freeze_controller.h>
11 #include <linux/delay.h>
12 #include <linux/errno.h>
14 static const struct socfpga_freeze_controller *freeze_controller_base =
15 (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
18 * Default state from cold reset is FREEZE_ALL; the global
19 * flag is set to TRUE to indicate the IO banks are frozen
21 static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
22 = { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
23 FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
26 void sys_mgr_frzctrl_freeze_req(void)
28 u32 ioctrl_reg_offset;
33 /* select software FSM */
34 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
36 /* Freeze channel 0 to 2 */
37 for (channel_id = 0; channel_id <= 2; channel_id++) {
38 ioctrl_reg_offset = (u32)(
39 &freeze_controller_base->vioctrl + channel_id);
42 * Assert active low enrnsl, plniotri
46 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
47 | SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
48 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
49 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
52 * Note: Delay for 20ns at min
53 * Assert active low bhniotri signal and de-assert
57 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
58 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
59 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask);
61 /* Set global flag to indicate channel is frozen */
62 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
65 /* Freeze channel 3 */
67 * Assert active low enrnsl, plniotri and
71 = SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
72 | SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
73 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
74 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
77 * assert active low bhniotri & nfrzdrv signals,
78 * de-assert active high csrdone and assert
79 * active high frzreg and nfrzdrv signals
81 reg_value = readl(&freeze_controller_base->hioctrl);
83 = SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
84 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
86 = (reg_value & ~reg_cfg_mask)
87 | SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
88 | SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
89 writel(reg_value, &freeze_controller_base->hioctrl);
92 * assert active high reinit signal and de-assert
93 * active high pllbiasen signals
95 reg_value = readl(&freeze_controller_base->hioctrl);
98 ~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
99 | SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
100 writel(reg_value, &freeze_controller_base->hioctrl);
102 /* Set global flag to indicate channel is frozen */
103 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
106 /* Unfreeze/Thaw HPS IOs */
107 void sys_mgr_frzctrl_thaw_req(void)
109 u32 ioctrl_reg_offset;
113 unsigned long eosc1_freq;
115 /* select software FSM */
116 writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src);
118 /* Thaw channel 0 to 2 */
119 for (channel_id = 0; channel_id <= 2; channel_id++) {
121 = (u32)(&freeze_controller_base->vioctrl + channel_id);
124 * Assert active low bhniotri signal and
125 * de-assert active high csrdone
128 = SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
129 | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
130 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
133 * Note: Delay for 20ns at min
134 * de-assert active low plniotri and niotri signals
137 = SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
138 | SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
139 setbits_le32(ioctrl_reg_offset, reg_cfg_mask);
142 * Note: Delay for 20ns at min
143 * de-assert active low enrnsl signal
145 setbits_le32(ioctrl_reg_offset,
146 SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
148 /* Set global flag to indicate channel is thawed */
149 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
153 /* de-assert active high reinit signal */
154 clrbits_le32(&freeze_controller_base->hioctrl,
155 SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
158 * Note: Delay for 40ns at min
159 * assert active high pllbiasen signals
161 setbits_le32(&freeze_controller_base->hioctrl,
162 SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
164 /* Delay 1000 intosc cycles. The intosc is based on eosc1. */
165 eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */
166 udelay(DIV_ROUND_UP(1000000, eosc1_freq));
169 * de-assert active low bhniotri signals,
170 * assert active high csrdone and nfrzdrv signal
172 reg_value = readl(&freeze_controller_base->hioctrl);
173 reg_value = (reg_value
174 | SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
175 | SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
176 & ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
177 writel(reg_value, &freeze_controller_base->hioctrl);
181 * Use worst case which is fatest eosc1=50MHz, delay required
182 * is 1/50MHz * 33 = 660ns ~= 1us
186 /* de-assert active low plniotri and niotri signals */
188 = SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
189 | SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
191 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
194 * Note: Delay for 40ns at min
195 * de-assert active high frzreg signal
197 clrbits_le32(&freeze_controller_base->hioctrl,
198 SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
201 * Note: Delay for 40ns at min
202 * de-assert active low enrnsl signal
204 setbits_le32(&freeze_controller_base->hioctrl,
205 SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
207 /* Set global flag to indicate channel is thawed */
208 frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;