arch/arm/mach-socfpga/clock_manager_n5x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <asm/arch/clock_manager.h>
   9 #include <asm/arch/system_manager.h>
  10 #include <asm/global_data.h>
  11 #include <asm/io.h>
  12 #include <clk.h>
  13 #include <dm.h>
  14 #include <dt-bindings/clock/n5x-clock.h>
  15 #include <malloc.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 static ulong cm_get_rate_dm(u32 id)
  20 {
  21         struct udevice *dev;
  22         struct clk clk;
  23         ulong rate;
  24         int ret;
  25
  26         ret = uclass_get_device_by_driver(UCLASS_CLK,
  27                                           DM_DRIVER_GET(socfpga_n5x_clk),
  28                                           &dev);
  29         if (ret)
  30                 return 0;
  31
  32         clk.id = id;
  33         ret = clk_request(dev, &clk);
  34         if (ret < 0)
  35                 return 0;
  36
  37         rate = clk_get_rate(&clk);
  38
  39         clk_free(&clk);
  40
  41         if ((rate == (unsigned long)-ENXIO) ||
  42             (rate == (unsigned long)-EIO)) {
  43                 debug("%s id %u: clk_get_rate err: %ld\n",
  44                       __func__, id, rate);
  45                 return 0;
  46         }
  47
  48         return rate;
  49 }
  50
  51 static u32 cm_get_rate_dm_khz(u32 id)
  52 {
  53         return cm_get_rate_dm(id) / 1000;
  54 }
  55
  56 unsigned long cm_get_mpu_clk_hz(void)
  57 {
  58         return cm_get_rate_dm(N5X_MPU_CLK);
  59 }
  60
  61 unsigned int cm_get_l4_sys_free_clk_hz(void)
  62 {
  63         return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
  64 }
  65
  66 void cm_print_clock_quick_summary(void)
  67 {
  68         printf("MPU       %10d kHz\n",
  69                cm_get_rate_dm_khz(N5X_MPU_CLK));
  70         printf("L4 Main     %8d kHz\n",
  71                cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
  72         printf("L4 sys free %8d kHz\n",
  73                cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
  74         printf("L4 MP       %8d kHz\n",
  75                cm_get_rate_dm_khz(N5X_L4_MP_CLK));
  76         printf("L4 SP       %8d kHz\n",
  77                cm_get_rate_dm_khz(N5X_L4_SP_CLK));
  78         printf("SDMMC       %8d kHz\n",
  79                cm_get_rate_dm_khz(N5X_SDMMC_CLK));
  80 }