arch/arm/mach-socfpga/clock_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <asm/io.h>
   9 #include <dm.h>
  10 #include <clk.h>
  11 #include <dm/device-internal.h>
  12 #include <asm/arch/clock_manager.h>
  13
  14 static const struct socfpga_clock_manager *clock_manager_base =
  15         (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  16
  17 static u32 eosc1_hz;
  18 static u32 cb_intosc_hz;
  19 static u32 f2s_free_hz;
  20
  21 struct mainpll_cfg {
  22         u32 vco0_psrc;
  23         u32 vco1_denom;
  24         u32 vco1_numer;
  25         u32 mpuclk;
  26         u32 mpuclk_cnt;
  27         u32 mpuclk_src;
  28         u32 nocclk;
  29         u32 nocclk_cnt;
  30         u32 nocclk_src;
  31         u32 cntr2clk_cnt;
  32         u32 cntr3clk_cnt;
  33         u32 cntr4clk_cnt;
  34         u32 cntr5clk_cnt;
  35         u32 cntr6clk_cnt;
  36         u32 cntr7clk_cnt;
  37         u32 cntr7clk_src;
  38         u32 cntr8clk_cnt;
  39         u32 cntr9clk_cnt;
  40         u32 cntr9clk_src;
  41         u32 cntr15clk_cnt;
  42         u32 nocdiv_l4mainclk;
  43         u32 nocdiv_l4mpclk;
  44         u32 nocdiv_l4spclk;
  45         u32 nocdiv_csatclk;
  46         u32 nocdiv_cstraceclk;
  47         u32 nocdiv_cspdbclk;
  48 };
  49
  50 struct perpll_cfg {
  51         u32 vco0_psrc;
  52         u32 vco1_denom;
  53         u32 vco1_numer;
  54         u32 cntr2clk_cnt;
  55         u32 cntr2clk_src;
  56         u32 cntr3clk_cnt;
  57         u32 cntr3clk_src;
  58         u32 cntr4clk_cnt;
  59         u32 cntr4clk_src;
  60         u32 cntr5clk_cnt;
  61         u32 cntr5clk_src;
  62         u32 cntr6clk_cnt;
  63         u32 cntr6clk_src;
  64         u32 cntr7clk_cnt;
  65         u32 cntr8clk_cnt;
  66         u32 cntr8clk_src;
  67         u32 cntr9clk_cnt;
  68         u32 cntr9clk_src;
  69         u32 emacctl_emac0sel;
  70         u32 emacctl_emac1sel;
  71         u32 emacctl_emac2sel;
  72         u32 gpiodiv_gpiodbclk;
  73 };
  74
  75 struct strtou32 {
  76         const char *str;
  77         const u32 val;
  78 };
  79
  80 static const struct strtou32 mainpll_cfg_tab[] = {
  81         { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) },
  82         { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) },
  83         { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) },
  84         { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) },
  85         { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) },
  86         { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) },
  87         { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) },
  88         { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) },
  89         { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) },
  90         { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) },
  91         { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) },
  92         { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) },
  93         { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) },
  94         { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) },
  95         { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) },
  96         { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) },
  97         { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) },
  98         { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) },
  99         { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) },
 100         { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) },
 101         { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) },
 102         { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) },
 103         { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) },
 104         { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) },
 105 };
 106
 107 static const struct strtou32 perpll_cfg_tab[] = {
 108         { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) },
 109         { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) },
 110         { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) },
 111         { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) },
 112         { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) },
 113         { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) },
 114         { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) },
 115         { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) },
 116         { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) },
 117         { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) },
 118         { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) },
 119         { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) },
 120         { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) },
 121         { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) },
 122         { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) },
 123         { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) },
 124         { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) },
 125         { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) },
 126         { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) },
 127         { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) },
 128         { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) },
 129 };
 130
 131 static const struct strtou32 alteragrp_cfg_tab[] = {
 132         { "nocclk", offsetof(struct mainpll_cfg, nocclk) },
 133         { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },
 134 };
 135
 136 struct strtopu32 {
 137         const char *str;
 138         u32 *p;
 139 };
 140
 141 const struct strtopu32 dt_to_val[] = {
 142         { "altera_arria10_hps_eosc1", &eosc1_hz },
 143         { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
 144         { "altera_arria10_hps_f2h_free", &f2s_free_hz },
 145 };
 146
 147 static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
 148                         int cfg_tab_len, void *cfg)
 149 {
 150         int i;
 151         u32 val;
 152
 153         for (i = 0; i < cfg_tab_len; i++) {
 154                 if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) {
 155                         /* could not find required property */
 156                         return -EINVAL;
 157                 }
 158                 *(u32 *)(cfg + cfg_tab[i].val) = val;
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int of_get_input_clks(const void *blob)
 165 {
 166         struct udevice *dev;
 167         struct clk clk;
 168         int i, ret;
 169
 170         for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
 171                 memset(&clk, 0, sizeof(clk));
 172
 173                 ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str,
 174                                                 &dev);
 175                 if (ret)
 176                         return ret;
 177
 178                 ret = clk_request(dev, &clk);
 179                 if (ret)
 180                         return ret;
 181
 182                 *dt_to_val[i].p = clk_get_rate(&clk);
 183         }
 184
 185         return 0;
 186 }
 187
 188 static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
 189                           struct perpll_cfg *per_cfg)
 190 {
 191         int ret, node, child, len;
 192         const char *node_name;
 193
 194         ret = of_get_input_clks(blob);
 195         if (ret)
 196                 return ret;
 197
 198         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
 199
 200         if (node < 0)
 201                 return -EINVAL;
 202
 203         child = fdt_first_subnode(blob, node);
 204
 205         if (child < 0)
 206                 return -EINVAL;
 207
 208         node_name = fdt_get_name(blob, child, &len);
 209
 210         while (node_name) {
 211                 if (!strcmp(node_name, "mainpll")) {
 212                         if (of_to_struct(blob, child, mainpll_cfg_tab,
 213                                          ARRAY_SIZE(mainpll_cfg_tab), main_cfg))
 214                                 return -EINVAL;
 215                 } else if (!strcmp(node_name, "perpll")) {
 216                         if (of_to_struct(blob, child, perpll_cfg_tab,
 217                                          ARRAY_SIZE(perpll_cfg_tab), per_cfg))
 218                                 return -EINVAL;
 219                 } else if (!strcmp(node_name, "alteragrp")) {
 220                         if (of_to_struct(blob, child, alteragrp_cfg_tab,
 221                                          ARRAY_SIZE(alteragrp_cfg_tab), main_cfg))
 222                                 return -EINVAL;
 223                 }
 224                 child = fdt_next_subnode(blob, child);
 225
 226                 if (child < 0)
 227                         break;
 228
 229                 node_name = fdt_get_name(blob, child, &len);
 230         }
 231
 232         return 0;
 233 }
 234
 235 /* calculate the intended main VCO frequency based on handoff */
 236 static unsigned int cm_calc_handoff_main_vco_clk_hz
 237                                         (struct mainpll_cfg *main_cfg)
 238 {
 239         unsigned int clk_hz;
 240
 241         /* Check main VCO clock source: eosc, intosc or f2s? */
 242         switch (main_cfg->vco0_psrc) {
 243         case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 244                 clk_hz = eosc1_hz;
 245                 break;
 246         case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 247                 clk_hz = cb_intosc_hz;
 248                 break;
 249         case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 250                 clk_hz = f2s_free_hz;
 251                 break;
 252         default:
 253                 return 0;
 254         }
 255
 256         /* calculate the VCO frequency */
 257         clk_hz /= 1 + main_cfg->vco1_denom;
 258         clk_hz *= 1 + main_cfg->vco1_numer;
 259
 260         return clk_hz;
 261 }
 262
 263 /* calculate the intended periph VCO frequency based on handoff */
 264 static unsigned int cm_calc_handoff_periph_vco_clk_hz(
 265                 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 266 {
 267         unsigned int clk_hz;
 268
 269         /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
 270         switch (per_cfg->vco0_psrc) {
 271         case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 272                 clk_hz = eosc1_hz;
 273                 break;
 274         case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 275                 clk_hz = cb_intosc_hz;
 276                 break;
 277         case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 278                 clk_hz = f2s_free_hz;
 279                 break;
 280         case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 281                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 282                 clk_hz /= main_cfg->cntr15clk_cnt;
 283                 break;
 284         default:
 285                 return 0;
 286         }
 287
 288         /* calculate the VCO frequency */
 289         clk_hz /= 1 + per_cfg->vco1_denom;
 290         clk_hz *= 1 + per_cfg->vco1_numer;
 291
 292         return clk_hz;
 293 }
 294
 295 /* calculate the intended MPU clock frequency based on handoff */
 296 static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
 297                                                struct perpll_cfg *per_cfg)
 298 {
 299         unsigned int clk_hz;
 300
 301         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 302         switch (main_cfg->mpuclk_src) {
 303         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 304                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 305                 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
 306                            + 1;
 307                 break;
 308         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 309                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 310                 clk_hz /= ((main_cfg->mpuclk >>
 311                            CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 312                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 313                 break;
 314         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 315                 clk_hz = eosc1_hz;
 316                 break;
 317         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 318                 clk_hz = cb_intosc_hz;
 319                 break;
 320         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 321                 clk_hz = f2s_free_hz;
 322                 break;
 323         default:
 324                 return 0;
 325         }
 326
 327         clk_hz /= main_cfg->mpuclk_cnt + 1;
 328         return clk_hz;
 329 }
 330
 331 /* calculate the intended NOC clock frequency based on handoff */
 332 static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
 333                                                struct perpll_cfg *per_cfg)
 334 {
 335         unsigned int clk_hz;
 336
 337         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 338         switch (main_cfg->nocclk_src) {
 339         case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
 340                 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 341                 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
 342                          + 1;
 343                 break;
 344         case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
 345                 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
 346                 clk_hz /= ((main_cfg->nocclk >>
 347                            CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 348                            CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
 349                 break;
 350         case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
 351                 clk_hz = eosc1_hz;
 352                 break;
 353         case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
 354                 clk_hz = cb_intosc_hz;
 355                 break;
 356         case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
 357                 clk_hz = f2s_free_hz;
 358                 break;
 359         default:
 360                 return 0;
 361         }
 362
 363         clk_hz /= main_cfg->nocclk_cnt + 1;
 364         return clk_hz;
 365 }
 366
 367 /* return 1 if PLL ramp is required */
 368 static int cm_is_pll_ramp_required(int main0periph1,
 369                                    struct mainpll_cfg *main_cfg,
 370                                    struct perpll_cfg *per_cfg)
 371 {
 372         /* Check for main PLL */
 373         if (main0periph1 == 0) {
 374                 /*
 375                  * PLL ramp is not required if both MPU clock and NOC clock are
 376                  * not sourced from main PLL
 377                  */
 378                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 379                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
 380                         return 0;
 381
 382                 /*
 383                  * PLL ramp is required if MPU clock is sourced from main PLL
 384                  * and MPU clock is over 900MHz (as advised by HW team)
 385                  */
 386                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
 387                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 388                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 389                         return 1;
 390
 391                 /*
 392                  * PLL ramp is required if NOC clock is sourced from main PLL
 393                  * and NOC clock is over 300MHz (as advised by HW team)
 394                  */
 395                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
 396                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 397                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 398                         return 2;
 399
 400         } else if (main0periph1 == 1) {
 401                 /*
 402                  * PLL ramp is not required if both MPU clock and NOC clock are
 403                  * not sourced from periph PLL
 404                  */
 405                 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 406                     main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
 407                         return 0;
 408
 409                 /*
 410                  * PLL ramp is required if MPU clock are source from periph PLL
 411                  * and MPU clock is over 900MHz (as advised by HW team)
 412                  */
 413                 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
 414                     (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
 415                      CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
 416                         return 1;
 417
 418                 /*
 419                  * PLL ramp is required if NOC clock are source from periph PLL
 420                  * and NOC clock is over 300MHz (as advised by HW team)
 421                  */
 422                 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
 423                     (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
 424                      CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
 425                         return 2;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
 432                               struct perpll_cfg *per_cfg,
 433                               u32 safe_hz, u32 clk_hz)
 434 {
 435         u32 cnt;
 436         u32 clk;
 437         u32 shift;
 438         u32 mask;
 439         u32 denom;
 440
 441         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 442                 cnt = main_cfg->mpuclk_cnt;
 443                 clk = main_cfg->mpuclk;
 444                 shift = 0;
 445                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 446                 denom = main_cfg->vco1_denom;
 447         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 448                 cnt = main_cfg->nocclk_cnt;
 449                 clk = main_cfg->nocclk;
 450                 shift = 0;
 451                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 452                 denom = main_cfg->vco1_denom;
 453         } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 454                 cnt = main_cfg->mpuclk_cnt;
 455                 clk = main_cfg->mpuclk;
 456                 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
 457                 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
 458                 denom = per_cfg->vco1_denom;
 459         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 460                 cnt = main_cfg->nocclk_cnt;
 461                 clk = main_cfg->nocclk;
 462                 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
 463                 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
 464                 denom = per_cfg->vco1_denom;
 465         } else {
 466                 return 0;
 467         }
 468
 469         return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
 470                 (1 + denom) - 1;
 471 }
 472
 473 /*
 474  * Calculate the new PLL numerator which is based on existing DTS hand off and
 475  * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
 476  * numerator while maintaining denominator as denominator will influence the
 477  * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
 478  * value for numerator is minus with 1 to cater our register value
 479  * representation.
 480  */
 481 static unsigned int cm_calc_safe_pll_numer(int main0periph1,
 482                                            struct mainpll_cfg *main_cfg,
 483                                            struct perpll_cfg *per_cfg,
 484                                            unsigned int safe_hz)
 485 {
 486         unsigned int clk_hz = 0;
 487
 488         /* Check for main PLL */
 489         if (main0periph1 == 0) {
 490                 /* Check main VCO clock source: eosc, intosc or f2s? */
 491                 switch (main_cfg->vco0_psrc) {
 492                 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
 493                         clk_hz = eosc1_hz;
 494                         break;
 495                 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
 496                         clk_hz = cb_intosc_hz;
 497                         break;
 498                 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
 499                         clk_hz = f2s_free_hz;
 500                         break;
 501                 default:
 502                         return 0;
 503                 }
 504         } else if (main0periph1 == 1) {
 505                 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
 506                 switch (per_cfg->vco0_psrc) {
 507                 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
 508                         clk_hz = eosc1_hz;
 509                         break;
 510                 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
 511                         clk_hz = cb_intosc_hz;
 512                         break;
 513                 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
 514                         clk_hz = f2s_free_hz;
 515                         break;
 516                 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
 517                         clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
 518                         clk_hz /= main_cfg->cntr15clk_cnt;
 519                         break;
 520                 default:
 521                         return 0;
 522                 }
 523         } else {
 524                 return 0;
 525         }
 526
 527         return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
 528 }
 529
 530 /* ramping the main PLL to final value */
 531 static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
 532                              struct perpll_cfg *per_cfg,
 533                              unsigned int pll_ramp_main_hz)
 534 {
 535         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 536
 537         /* find out the increment value */
 538         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
 539                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 540                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 541         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
 542                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 543                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 544         }
 545
 546         /* execute the ramping here */
 547         for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
 548              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 549                 writel((main_cfg->vco1_denom <<
 550                         CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 551                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
 552                         &clock_manager_base->main_pll.vco1);
 553                 mdelay(1);
 554                 cm_wait_for_lock(LOCKED_MASK);
 555         }
 556         writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 557                 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
 558         mdelay(1);
 559         cm_wait_for_lock(LOCKED_MASK);
 560 }
 561
 562 /* ramping the periph PLL to final value */
 563 static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
 564                                struct perpll_cfg *per_cfg,
 565                                unsigned int pll_ramp_periph_hz)
 566 {
 567         unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
 568
 569         /* find out the increment value */
 570         if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
 571                 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
 572                 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
 573         } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
 574                 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
 575                 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
 576         }
 577         /* execute the ramping here */
 578         for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
 579              clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
 580                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 581                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
 582                         &clock_manager_base->per_pll.vco1);
 583                 mdelay(1);
 584                 cm_wait_for_lock(LOCKED_MASK);
 585         }
 586         writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 587                 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
 588         mdelay(1);
 589         cm_wait_for_lock(LOCKED_MASK);
 590 }
 591
 592 /*
 593  * Setup clocks while making no assumptions of the
 594  * previous state of the clocks.
 595  *
 596  * Start by being paranoid and gate all sw managed clocks
 597  *
 598  * Put all plls in bypass
 599  *
 600  * Put all plls VCO registers back to reset value (bgpwr dwn).
 601  *
 602  * Put peripheral and main pll src to reset value to avoid glitch.
 603  *
 604  * Delay 5 us.
 605  *
 606  * Deassert bg pwr dn and set numerator and denominator
 607  *
 608  * Start 7 us timer.
 609  *
 610  * set internal dividers
 611  *
 612  * Wait for 7 us timer.
 613  *
 614  * Enable plls
 615  *
 616  * Set external dividers while plls are locking
 617  *
 618  * Wait for pll lock
 619  *
 620  * Assert/deassert outreset all.
 621  *
 622  * Take all pll's out of bypass
 623  *
 624  * Clear safe mode
 625  *
 626  * set source main and peripheral clocks
 627  *
 628  * Ungate clocks
 629  */
 630
 631 static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
 632 {
 633         unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
 634                 ramp_required;
 635
 636         /* gate off all mainpll clock excpet HW managed clock */
 637         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 638                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 639                 &clock_manager_base->main_pll.enr);
 640
 641         /* now we can gate off the rest of the peripheral clocks */
 642         writel(0, &clock_manager_base->per_pll.en);
 643
 644         /* Put all plls in external bypass */
 645         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 646                &clock_manager_base->main_pll.bypasss);
 647         writel(CLKMGR_PERPLL_BYPASS_RESET,
 648                &clock_manager_base->per_pll.bypasss);
 649
 650         /*
 651          * Put all plls VCO registers back to reset value.
 652          * Some code might have messed with them. At same time set the
 653          * desired clock source
 654          */
 655         writel(CLKMGR_MAINPLL_VCO0_RESET |
 656                CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
 657                (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
 658                &clock_manager_base->main_pll.vco0);
 659
 660         writel(CLKMGR_PERPLL_VCO0_RESET |
 661                CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
 662                (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
 663                &clock_manager_base->per_pll.vco0);
 664
 665         writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
 666         writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
 667
 668         /* clear the interrupt register status register */
 669         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 670                 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 671                 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 672                 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 673                 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 674                 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
 675                 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
 676                 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
 677                 &clock_manager_base->intr);
 678
 679         /* Program VCO Numerator and Denominator for main PLL */
 680         ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
 681         if (ramp_required) {
 682                 /* set main PLL to safe starting threshold frequency */
 683                 if (ramp_required == 1)
 684                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 685                 else if (ramp_required == 2)
 686                         pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 687
 688                 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 689                         cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
 690                                                pll_ramp_main_hz),
 691                         &clock_manager_base->main_pll.vco1);
 692         } else
 693                 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
 694                         main_cfg->vco1_numer,
 695                         &clock_manager_base->main_pll.vco1);
 696
 697         /* Program VCO Numerator and Denominator for periph PLL */
 698         ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
 699         if (ramp_required) {
 700                 /* set periph PLL to safe starting threshold frequency */
 701                 if (ramp_required == 1)
 702                         pll_ramp_periph_hz =
 703                                 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
 704                 else if (ramp_required == 2)
 705                         pll_ramp_periph_hz =
 706                                 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
 707
 708                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 709                         cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
 710                                                pll_ramp_periph_hz),
 711                         &clock_manager_base->per_pll.vco1);
 712         } else
 713                 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
 714                         per_cfg->vco1_numer,
 715                         &clock_manager_base->per_pll.vco1);
 716
 717         /* Wait for at least 5 us */
 718         udelay(5);
 719
 720         /* Now deassert BGPWRDN and PWRDN */
 721         clrbits_le32(&clock_manager_base->main_pll.vco0,
 722                      CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
 723                      CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
 724         clrbits_le32(&clock_manager_base->per_pll.vco0,
 725                      CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
 726                      CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 727
 728         /* Wait for at least 7 us */
 729         udelay(7);
 730
 731         /* enable the VCO and disable the external regulator to PLL */
 732         writel((readl(&clock_manager_base->main_pll.vco0) &
 733                 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
 734                 CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
 735                 &clock_manager_base->main_pll.vco0);
 736         writel((readl(&clock_manager_base->per_pll.vco0) &
 737                 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
 738                 CLKMGR_PERPLL_VCO0_EN_SET_MSK,
 739                 &clock_manager_base->per_pll.vco0);
 740
 741         /* setup all the main PLL counter and clock source */
 742         writel(main_cfg->nocclk,
 743                SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
 744         writel(main_cfg->mpuclk,
 745                SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
 746
 747         /* main_emaca_clk divider */
 748         writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
 749         /* main_emacb_clk divider */
 750         writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
 751         /* main_emac_ptp_clk divider */
 752         writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
 753         /* main_gpio_db_clk divider */
 754         writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
 755         /* main_sdmmc_clk divider */
 756         writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
 757         /* main_s2f_user0_clk divider */
 758         writel(main_cfg->cntr7clk_cnt |
 759                (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
 760                &clock_manager_base->main_pll.cntr7clk);
 761         /* main_s2f_user1_clk divider */
 762         writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
 763         /* main_hmc_pll_clk divider */
 764         writel(main_cfg->cntr9clk_cnt |
 765                (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
 766                &clock_manager_base->main_pll.cntr9clk);
 767         /* main_periph_ref_clk divider */
 768         writel(main_cfg->cntr15clk_cnt,
 769                &clock_manager_base->main_pll.cntr15clk);
 770
 771         /* setup all the peripheral PLL counter and clock source */
 772         /* peri_emaca_clk divider */
 773         writel(per_cfg->cntr2clk_cnt |
 774                (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
 775                &clock_manager_base->per_pll.cntr2clk);
 776         /* peri_emacb_clk divider */
 777         writel(per_cfg->cntr3clk_cnt |
 778                (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
 779                &clock_manager_base->per_pll.cntr3clk);
 780         /* peri_emac_ptp_clk divider */
 781         writel(per_cfg->cntr4clk_cnt |
 782                (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
 783                &clock_manager_base->per_pll.cntr4clk);
 784         /* peri_gpio_db_clk divider */
 785         writel(per_cfg->cntr5clk_cnt |
 786                (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
 787                &clock_manager_base->per_pll.cntr5clk);
 788         /* peri_sdmmc_clk divider */
 789         writel(per_cfg->cntr6clk_cnt |
 790                (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
 791                &clock_manager_base->per_pll.cntr6clk);
 792         /* peri_s2f_user0_clk divider */
 793         writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
 794         /* peri_s2f_user1_clk divider */
 795         writel(per_cfg->cntr8clk_cnt |
 796                (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
 797                &clock_manager_base->per_pll.cntr8clk);
 798         /* peri_hmc_pll_clk divider */
 799         writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
 800
 801         /* setup all the external PLL counter */
 802         /* mpu wrapper / external divider */
 803         writel(main_cfg->mpuclk_cnt |
 804                (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
 805                &clock_manager_base->main_pll.mpuclk);
 806         /* NOC wrapper / external divider */
 807         writel(main_cfg->nocclk_cnt |
 808                (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
 809                &clock_manager_base->main_pll.nocclk);
 810         /* NOC subclock divider such as l4 */
 811         writel(main_cfg->nocdiv_l4mainclk |
 812                (main_cfg->nocdiv_l4mpclk <<
 813                 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
 814                (main_cfg->nocdiv_l4spclk <<
 815                 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
 816                (main_cfg->nocdiv_csatclk <<
 817                 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
 818                (main_cfg->nocdiv_cstraceclk <<
 819                 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
 820                (main_cfg->nocdiv_cspdbclk <<
 821                 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
 822                 &clock_manager_base->main_pll.nocdiv);
 823         /* gpio_db external divider */
 824         writel(per_cfg->gpiodiv_gpiodbclk,
 825                &clock_manager_base->per_pll.gpiodiv);
 826
 827         /* setup the EMAC clock mux select */
 828         writel((per_cfg->emacctl_emac0sel <<
 829                 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
 830                (per_cfg->emacctl_emac1sel <<
 831                 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
 832                (per_cfg->emacctl_emac2sel <<
 833                 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
 834                &clock_manager_base->per_pll.emacctl);
 835
 836         /* at this stage, check for PLL lock status */
 837         cm_wait_for_lock(LOCKED_MASK);
 838
 839         /*
 840          * after locking, but before taking out of bypass,
 841          * assert/deassert outresetall
 842          */
 843         /* assert mainpll outresetall */
 844         setbits_le32(&clock_manager_base->main_pll.vco0,
 845                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 846         /* assert perpll outresetall */
 847         setbits_le32(&clock_manager_base->per_pll.vco0,
 848                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 849         /* de-assert mainpll outresetall */
 850         clrbits_le32(&clock_manager_base->main_pll.vco0,
 851                      CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
 852         /* de-assert perpll outresetall */
 853         clrbits_le32(&clock_manager_base->per_pll.vco0,
 854                      CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
 855
 856         /* Take all PLLs out of bypass when boot mode is cleared. */
 857         /* release mainpll from bypass */
 858         writel(CLKMGR_MAINPLL_BYPASS_RESET,
 859                &clock_manager_base->main_pll.bypassr);
 860         /* wait till Clock Manager is not busy */
 861         cm_wait_for_fsm();
 862
 863         /* release perpll from bypass */
 864         writel(CLKMGR_PERPLL_BYPASS_RESET,
 865                &clock_manager_base->per_pll.bypassr);
 866         /* wait till Clock Manager is not busy */
 867         cm_wait_for_fsm();
 868
 869         /* clear boot mode */
 870         clrbits_le32(&clock_manager_base->ctrl,
 871                      CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
 872         /* wait till Clock Manager is not busy */
 873         cm_wait_for_fsm();
 874
 875         /* At here, we need to ramp to final value if needed */
 876         if (pll_ramp_main_hz != 0)
 877                 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
 878         if (pll_ramp_periph_hz != 0)
 879                 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
 880
 881         /* Now ungate non-hw-managed clocks */
 882         writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
 883                 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
 884                 &clock_manager_base->main_pll.ens);
 885         writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
 886
 887         /* Clear the loss lock and slip bits as they might set during
 888         clock reconfiguration */
 889         writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
 890                CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
 891                CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
 892                CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
 893                CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
 894                CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
 895                &clock_manager_base->intr);
 896
 897         return 0;
 898 }
 899
 900 void cm_use_intosc(void)
 901 {
 902         setbits_le32(&clock_manager_base->ctrl,
 903                      CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
 904 }
 905
 906 unsigned int cm_get_noc_clk_hz(void)
 907 {
 908         unsigned int clk_src, divisor, nocclk, src_hz;
 909
 910         nocclk = readl(&clock_manager_base->main_pll.nocclk);
 911         clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) &
 912                   CLKMGR_MAINPLL_NOCCLK_SRC_MSK;
 913
 914         divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK);
 915
 916         if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) {
 917                 src_hz = cm_get_main_vco_clk_hz();
 918                 src_hz /= 1 +
 919                 (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) &
 920                 CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
 921         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) {
 922                 src_hz = cm_get_per_vco_clk_hz();
 923                 src_hz /= 1 +
 924                 ((readl(SOCFPGA_CLKMGR_ADDRESS +
 925                         CLKMGR_MAINPLL_NOC_CLK_OFFSET) >>
 926                         CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
 927                         CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
 928         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) {
 929                 src_hz = eosc1_hz;
 930         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) {
 931                 src_hz = cb_intosc_hz;
 932         } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) {
 933                 src_hz = f2s_free_hz;
 934         } else {
 935                 src_hz = 0;
 936         }
 937
 938         return src_hz / divisor;
 939 }
 940
 941 unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift)
 942 {
 943         unsigned int divisor2 = 1 <<
 944                 ((readl(&clock_manager_base->main_pll.nocdiv) >>
 945                         nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK);
 946
 947         return cm_get_noc_clk_hz() / divisor2;
 948 }
 949
 950 int cm_basic_init(const void *blob)
 951 {
 952         struct mainpll_cfg main_cfg;
 953         struct perpll_cfg per_cfg;
 954         int rval;
 955
 956         /* initialize to zero for use case of optional node */
 957         memset(&main_cfg, 0, sizeof(main_cfg));
 958         memset(&per_cfg, 0, sizeof(per_cfg));
 959
 960         rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg);
 961         if (rval)
 962                 return rval;
 963
 964         return cm_full_cfg(&main_cfg, &per_cfg);
 965 }
 966
 967 unsigned long cm_get_mpu_clk_hz(void)
 968 {
 969         u32 reg, clk_hz;
 970         u32 clk_src, mainmpuclk_reg;
 971
 972         mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk);
 973
 974         clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) &
 975                 CLKMGR_MAINPLL_MPUCLK_SRC_MSK;
 976
 977         reg = readl(&clock_manager_base->altera.mpuclk);
 978         /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
 979         switch (clk_src) {
 980         case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
 981                 clk_hz = cm_get_main_vco_clk_hz();
 982                 clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
 983                 break;
 984         case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
 985                 clk_hz = cm_get_per_vco_clk_hz();
 986                 clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
 987                            CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
 988                 break;
 989         case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
 990                 clk_hz = eosc1_hz;
 991                 break;
 992         case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
 993                 clk_hz = cb_intosc_hz;
 994                 break;
 995         case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
 996                 clk_hz = f2s_free_hz;
 997                 break;
 998         default:
 999                 printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src);
1000                 return 0;
1001         }
1002
1003         clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
1004
1005         return clk_hz;
1006 }
1007
1008 unsigned int cm_get_per_vco_clk_hz(void)
1009 {
1010         u32 src_hz = 0;
1011         u32 clk_src = 0;
1012         u32 numer = 0;
1013         u32 denom = 0;
1014         u32 vco = 0;
1015
1016         clk_src = readl(&clock_manager_base->per_pll.vco0);
1017
1018         clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) &
1019                 CLKMGR_PERPLL_VCO0_PSRC_MSK;
1020
1021         if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) {
1022                 src_hz = eosc1_hz;
1023         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {
1024                 src_hz = cb_intosc_hz;
1025         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) {
1026                 src_hz = f2s_free_hz;
1027         } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) {
1028                 src_hz = cm_get_main_vco_clk_hz();
1029                 src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) &
1030                         CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
1031         } else {
1032                 printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src);
1033                 return 0;
1034         }
1035
1036         vco = readl(&clock_manager_base->per_pll.vco1);
1037
1038         numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK;
1039
1040         denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
1041                         CLKMGR_PERPLL_VCO1_DENOM_MSK;
1042
1043         vco = src_hz;
1044         vco /= 1 + denom;
1045         vco *= 1 + numer;
1046
1047         return vco;
1048 }
1049
1050 unsigned int cm_get_main_vco_clk_hz(void)
1051 {
1052         u32 src_hz, numer, denom, vco;
1053
1054         u32 clk_src = readl(&clock_manager_base->main_pll.vco0);
1055
1056         clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
1057                 CLKMGR_MAINPLL_VCO0_PSRC_MSK;
1058
1059         if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {
1060                 src_hz = eosc1_hz;
1061         } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {
1062                 src_hz = cb_intosc_hz;
1063         } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) {
1064                 src_hz = f2s_free_hz;
1065         } else {
1066                 printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src);
1067                 return 0;
1068         }
1069
1070         vco = readl(&clock_manager_base->main_pll.vco1);
1071
1072         numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
1073
1074         denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
1075                         CLKMGR_MAINPLL_VCO1_DENOM_MSK;
1076
1077         vco = src_hz;
1078         vco /= 1 + denom;
1079         vco *= 1 + numer;
1080
1081         return vco;
1082 }
1083
1084 unsigned int cm_get_l4_sp_clk_hz(void)
1085 {
1086         return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB);
1087 }
1088
1089 unsigned int cm_get_mmc_controller_clk_hz(void)
1090 {
1091         u32 clk_hz = 0;
1092         u32 clk_input = 0;
1093
1094         clk_input = readl(&clock_manager_base->per_pll.cntr6clk);
1095         clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
1096                 CLKMGR_PERPLLGRP_SRC_MSK;
1097
1098         switch (clk_input) {
1099         case CLKMGR_PERPLLGRP_SRC_MAIN:
1100                 clk_hz = cm_get_main_vco_clk_hz();
1101                 clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
1102                         CLKMGR_MAINPLL_CNTRCLK_MSK);
1103                 break;
1104
1105         case CLKMGR_PERPLLGRP_SRC_PERI:
1106                 clk_hz = cm_get_per_vco_clk_hz();
1107                 clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
1108                         CLKMGR_PERPLL_CNTRCLK_MSK);
1109                 break;
1110
1111         case CLKMGR_PERPLLGRP_SRC_OSC1:
1112                 clk_hz = eosc1_hz;
1113                 break;
1114
1115         case CLKMGR_PERPLLGRP_SRC_INTOSC:
1116                 clk_hz = cb_intosc_hz;
1117                 break;
1118
1119         case CLKMGR_PERPLLGRP_SRC_FPGA:
1120                 clk_hz = f2s_free_hz;
1121                 break;
1122         }
1123
1124         return clk_hz / 4;
1125 }
1126
1127 unsigned int cm_get_spi_controller_clk_hz(void)
1128 {
1129         return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
1130 }
1131
1132 unsigned int cm_get_qspi_controller_clk_hz(void)
1133 {
1134         return  cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
1135 }
1136
1137 /* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
1138 int dw_spi_get_clk(struct udevice *bus, ulong *rate)
1139 {
1140         *rate = cm_get_spi_controller_clk_hz();
1141
1142         return 0;
1143 }
1144
1145 void cm_print_clock_quick_summary(void)
1146 {
1147         printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
1148         printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
1149         printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
1150         printf("SPI         %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
1151         printf("EOSC1       %8d kHz\n", eosc1_hz / 1000);
1152         printf("cb_intosc   %8d kHz\n", cb_intosc_hz / 1000);
1153         printf("f2s_free    %8d kHz\n", f2s_free_hz / 1000);
1154         printf("Main VCO    %8d kHz\n", cm_get_main_vco_clk_hz() / 1000);
1155         printf("NOC         %8d kHz\n", cm_get_noc_clk_hz() / 1000);
1156         printf("L4 Main     %8d kHz\n",
1157                cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000);
1158         printf("L4 MP       %8d kHz\n",
1159                cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
1160         printf("L4 SP       %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
1161         printf("L4 sys free %8d kHz\n", cm_get_noc_clk_hz() / 4000);
1162 }