1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
12 #include <asm/arch/clock_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/global_data.h>
16 #include <dt-bindings/clock/agilex-clock.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 static ulong cm_get_rate_dm(u32 id)
27 ret = uclass_get_device_by_driver(UCLASS_CLK,
28 DM_DRIVER_GET(socfpga_agilex_clk),
34 ret = clk_request(dev, &clk);
38 rate = clk_get_rate(&clk);
42 if ((rate == (unsigned long)-ENOSYS) ||
43 (rate == (unsigned long)-ENXIO) ||
44 (rate == (unsigned long)-EIO)) {
45 debug("%s id %u: clk_get_rate err: %ld\n",
53 static u32 cm_get_rate_dm_khz(u32 id)
55 return cm_get_rate_dm(id) / 1000;
58 unsigned long cm_get_mpu_clk_hz(void)
60 return cm_get_rate_dm(AGILEX_MPU_CLK);
63 unsigned int cm_get_l4_sys_free_clk_hz(void)
65 return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
68 void cm_print_clock_quick_summary(void)
70 printf("MPU %10d kHz\n",
71 cm_get_rate_dm_khz(AGILEX_MPU_CLK));
72 printf("L4 Main %8d kHz\n",
73 cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
74 printf("L4 sys free %8d kHz\n",
75 cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
76 printf("L4 MP %8d kHz\n",
77 cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
78 printf("L4 SP %8d kHz\n",
79 cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
80 printf("SDMMC %8d kHz\n",
81 cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));