1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
10 #include <asm/global_data.h>
12 #include <asm/arch/clock_manager.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 void cm_wait_for_lock(u32 mask)
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 inter_val = readl(socfpga_get_clkmgr_addr() +
25 inter_val = readl(socfpga_get_clkmgr_addr() +
28 /* Wait for stable lock */
29 if (inter_val == mask)
38 /* function to poll in the fsm busy bit */
39 int cm_wait_for_fsm(void)
41 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
42 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
46 int set_cpu_clk_info(void)
48 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
49 /* Calculate the clock frequencies required for drivers */
50 cm_get_l4_sp_clk_hz();
51 cm_get_mmc_controller_clk_hz();
54 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
55 gd->bd->bi_dsp_freq = 0;
57 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
58 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
60 gd->bd->bi_ddr_freq = 0;
66 #ifndef CONFIG_SPL_BUILD
67 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
70 cm_print_clock_quick_summary();
75 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,