1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
10 #include <asm/arch/clock_manager.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 void cm_wait_for_lock(u32 mask)
19 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
20 inter_val = readl(socfpga_get_clkmgr_addr() +
23 inter_val = readl(socfpga_get_clkmgr_addr() +
26 /* Wait for stable lock */
27 if (inter_val == mask)
36 /* function to poll in the fsm busy bit */
37 int cm_wait_for_fsm(void)
39 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
40 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
44 int set_cpu_clk_info(void)
46 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
47 /* Calculate the clock frequencies required for drivers */
48 cm_get_l4_sp_clk_hz();
49 cm_get_mmc_controller_clk_hz();
52 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
53 gd->bd->bi_dsp_freq = 0;
55 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
56 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
58 gd->bd->bi_ddr_freq = 0;
64 #ifndef CONFIG_SPL_BUILD
65 static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
67 cm_print_clock_quick_summary();
72 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,