1 // SPDX-License-Identifier: GPL-2.0+
3 * Altera SoCFPGA common board code
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/clock_manager.h>
14 #include <asm/arch/misc.h>
15 #include <asm/global_data.h>
19 #include <usb/dwc2_udc.h>
21 DECLARE_GLOBAL_DATA_PTR;
26 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
27 * is disabled in ACTLR.
28 * This is optional on CycloneV / ArriaV.
29 * This is mandatory on Arria10, otherwise Linux refuses to boot.
32 "mcr p15, 0, %0, c1, c0, 1\n"
33 "mcr p15, 0, %0, c1, c0, 2\n"
41 * Miscellaneous platform dependent initialisations
45 /* Address of boot parameters for ATAG (if ATAG is used) */
46 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
51 int dram_init_banksize(void)
53 fdtdec_setup_memory_banksize();
58 #ifdef CONFIG_USB_GADGET
59 struct dwc2_plat_otg_data socfpga_otg_data = {
60 .usb_gusbcfg = 0x1417,
63 int board_usb_init(int index, enum usb_init_type init)
68 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
69 COMPAT_ALTERA_SOCFPGA_DWC2USB,
71 if (count <= 0) /* No controller found. */
74 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
75 if (addr == FDT_ADDR_T_NONE) {
76 printf("UDC Controller has no 'reg' property!\n");
80 /* Patch the address from OF into the controller pdata. */
81 socfpga_otg_data.regs_otg = addr;
83 return dwc2_udc_probe(&socfpga_otg_data);
86 int g_dnl_board_usb_cable_connected(void)
92 #ifdef CONFIG_SPL_BUILD
93 __weak int board_fit_config_name_match(const char *name)
95 /* Just empty function now - can't decide what to choose */
96 debug("%s: %s\n", __func__, name);