arch/arm/mach-socfpga/Makefile

   1 # SPDX-License-Identifier: GPL-2.0+
   2 #
   3 # (C) Copyright 2000-2003
   4 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 #
   6 # Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
   7 # Copyright (C) 2017-2021 Intel Corporation <www.intel.com>
   8
   9 obj-y   += board.o
  10 obj-y   += clock_manager.o
  11 obj-y   += misc.o
  12
  13 ifdef CONFIG_TARGET_SOCFPGA_GEN5
  14 obj-y   += clock_manager_gen5.o
  15 obj-y   += misc_gen5.o
  16 obj-y   += reset_manager_gen5.o
  17 obj-y   += scan_manager.o
  18 obj-y   += system_manager_gen5.o
  19 obj-y   += timer.o
  20 obj-y   += wrap_pll_config.o
  21 obj-y   += fpga_manager.o
  22 endif
  23
  24 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
  25 obj-y   += clock_manager_arria10.o
  26 obj-y   += misc_arria10.o
  27 obj-y   += pinmux_arria10.o
  28 obj-y   += reset_manager_arria10.o
  29 endif
  30
  31 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
  32 obj-y   += clock_manager_s10.o
  33 obj-y   += lowlevel_init_soc64.o
  34 obj-y   += mailbox_s10.o
  35 obj-y   += misc_soc64.o
  36 obj-y   += mmu-arm64_s10.o
  37 obj-y   += reset_manager_s10.o
  38 obj-y   += system_manager_soc64.o
  39 obj-y   += timer_s10.o
  40 obj-y   += wrap_handoff_soc64.o
  41 obj-y   += wrap_pll_config_soc64.o
  42 endif
  43
  44 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  45 obj-y   += clock_manager_agilex.o
  46 obj-y   += lowlevel_init_soc64.o
  47 obj-y   += mailbox_s10.o
  48 obj-y   += misc_soc64.o
  49 obj-y   += mmu-arm64_s10.o
  50 obj-y   += reset_manager_s10.o
  51 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)   += secure_vab.o
  52 obj-y   += system_manager_soc64.o
  53 obj-y   += timer_s10.o
  54 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)   += vab.o
  55 obj-y   += wrap_handoff_soc64.o
  56 obj-y   += wrap_pll_config_soc64.o
  57 endif
  58
  59 ifdef CONFIG_TARGET_SOCFPGA_N5X
  60 obj-y   += clock_manager_n5x.o
  61 obj-y   += lowlevel_init_soc64.o
  62 obj-y   += mailbox_s10.o
  63 obj-y   += misc_soc64.o
  64 obj-y   += mmu-arm64_s10.o
  65 obj-y   += reset_manager_s10.o
  66 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)   += secure_vab.o
  67 obj-y   += system_manager_soc64.o
  68 obj-y   += timer_s10.o
  69 obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH)   += vab.o
  70 obj-y   += wrap_handoff_soc64.o
  71 obj-y   += wrap_pll_config_soc64.o
  72 endif
  73
  74 ifdef CONFIG_SPL_BUILD
  75 ifdef CONFIG_TARGET_SOCFPGA_GEN5
  76 obj-y   += spl_gen5.o
  77 obj-y   += freeze_controller.o
  78 obj-y   += wrap_iocsr_config.o
  79 obj-y   += wrap_pinmux_config.o
  80 obj-y   += wrap_sdram_config.o
  81 endif
  82 ifdef CONFIG_TARGET_SOCFPGA_SOC64
  83 obj-y   += firewall.o
  84 obj-y   += spl_soc64.o
  85 endif
  86 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
  87 obj-y   += spl_a10.o
  88 endif
  89 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
  90 obj-y   += spl_s10.o
  91 endif
  92 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  93 obj-y   += spl_agilex.o
  94 endif
  95 ifdef CONFIG_TARGET_SOCFPGA_N5X
  96 obj-y   += spl_n5x.o
  97 endif
  98 else
  99 obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
 100 obj-$(CONFIG_SPL_ATF) += smc_api.o
 101 endif
 102
 103 ifdef CONFIG_TARGET_SOCFPGA_GEN5
 104 # QTS-generated config file wrappers
 105 CFLAGS_wrap_iocsr_config.o      += -I$(srctree)/board/$(BOARDDIR)
 106 CFLAGS_wrap_pinmux_config.o     += -I$(srctree)/board/$(BOARDDIR)
 107 CFLAGS_wrap_pll_config.o        += -I$(srctree)/board/$(BOARDDIR)
 108 CFLAGS_wrap_sdram_config.o      += -I$(srctree)/board/$(BOARDDIR)
 109 endif