arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SOCFPGA_SECURE_VAB_AUTH
  10         bool "Enable boot image authentication with Secure Device Manager"
  11         depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
  12           TARGET_SOCFPGA_AGILEX5
  13         select FIT_IMAGE_POST_PROCESS
  14         select SHA384
  15         select SHA512
  16         select SPL_FIT_IMAGE_POST_PROCESS
  17         help
  18          All images loaded from FIT will be authenticated by Secure Device
  19          Manager.
  20
  21 config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
  22         bool "Allow non-FIT VAB signed images"
  23         depends on SOCFPGA_SECURE_VAB_AUTH
  24
  25 config SPL_SIZE_LIMIT
  26         default 0x10000 if TARGET_SOCFPGA_GEN5
  27
  28 config SPL_SIZE_LIMIT_PROVIDE_STACK
  29         default 0x200 if TARGET_SOCFPGA_GEN5
  30
  31 config SPL_STACK_R_ADDR
  32         default 0x00800000 if TARGET_SOCFPGA_GEN5
  33
  34 config SPL_SYS_MALLOC_F
  35         default y if TARGET_SOCFPGA_GEN5
  36
  37 config SPL_SYS_MALLOC_F_LEN
  38         default 0x800 if TARGET_SOCFPGA_GEN5
  39
  40 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  41         default 0xa2
  42
  43 config SYS_MALLOC_F_LEN
  44         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  45         default 0x2000 if TARGET_SOCFPGA_GEN5
  46
  47 config TEXT_BASE
  48         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  49         default 0x01000040 if TARGET_SOCFPGA_GEN5
  50
  51 config TARGET_SOCFPGA_AGILEX
  52         bool
  53         select ARMV8_MULTIENTRY
  54         select ARMV8_SET_SMPEN
  55         select BINMAN if SPL_ATF
  56         select CLK
  57         select FPGA_INTEL_SDM_MAILBOX
  58         select NCORE_CACHE
  59         select SPL_CLK if SPL
  60         select TARGET_SOCFPGA_SOC64
  61
  62 config TARGET_SOCFPGA_AGILEX5
  63         bool
  64         select BINMAN if SPL_ATF
  65         select CLK
  66         select FPGA_INTEL_SDM_MAILBOX
  67         select GICV3
  68         select SPL_CLK if SPL
  69         select TARGET_SOCFPGA_SOC64
  70
  71 config TARGET_SOCFPGA_ARRIA5
  72         bool
  73         select TARGET_SOCFPGA_GEN5
  74
  75 config TARGET_SOCFPGA_ARRIA10
  76         bool
  77         select SPL_ALTERA_SDRAM
  78         select SPL_BOARD_INIT if SPL
  79         select SPL_CACHE if SPL
  80         select CLK
  81         select SPL_CLK if SPL
  82         select DM_I2C
  83         select DM_RESET
  84         select SPL_DM_RESET if SPL
  85         select REGMAP
  86         select SPL_REGMAP if SPL
  87         select SYSCON
  88         select SPL_SYSCON if SPL
  89         select ETH_DESIGNWARE_SOCFPGA
  90         imply FPGA_SOCFPGA
  91         imply SPL_USE_TINY_PRINTF
  92
  93 config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
  94         bool "Always reprogram Arria 10 FPGA"
  95         depends on TARGET_SOCFPGA_ARRIA10
  96         help
  97           Arria 10 FPGA is only programmed during the cold boot.
  98           This option forces the FPGA to be reprogrammed every reboot,
  99           allowing to change the bitstream and apply it with warm reboot.
 100
 101 config TARGET_SOCFPGA_CYCLONE5
 102         bool
 103         select TARGET_SOCFPGA_GEN5
 104
 105 config TARGET_SOCFPGA_GEN5
 106         bool
 107         select SPL_ALTERA_SDRAM
 108         imply FPGA_SOCFPGA
 109         imply SPL_SIZE_LIMIT_SUBTRACT_GD
 110         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
 111         imply SPL_STACK_R
 112         imply SPL_SYS_MALLOC_SIMPLE
 113         imply SPL_USE_TINY_PRINTF
 114
 115 config TARGET_SOCFPGA_N5X
 116         bool
 117         select ARMV8_MULTIENTRY
 118         select ARMV8_SET_SMPEN
 119         select BINMAN if SPL_ATF
 120         select CLK
 121         select FPGA_INTEL_SDM_MAILBOX
 122         select NCORE_CACHE
 123         select SPL_ALTERA_SDRAM
 124         select SPL_CLK if SPL
 125         select TARGET_SOCFPGA_SOC64
 126
 127 config TARGET_SOCFPGA_N5X_SOCDK
 128         bool "Intel eASIC SoCDK (N5X)"
 129         select TARGET_SOCFPGA_N5X
 130
 131 config TARGET_SOCFPGA_SOC64
 132         bool
 133
 134 config TARGET_SOCFPGA_STRATIX10
 135         bool
 136         select ARMV8_MULTIENTRY
 137         select ARMV8_SET_SMPEN
 138         select BINMAN if SPL_ATF
 139         select FPGA_INTEL_SDM_MAILBOX
 140         select TARGET_SOCFPGA_SOC64
 141
 142 choice
 143         prompt "Altera SOCFPGA board select"
 144         optional
 145
 146 config TARGET_SOCFPGA_AGILEX_SOCDK
 147         bool "Intel SOCFPGA SoCDK (Agilex)"
 148         select TARGET_SOCFPGA_AGILEX
 149
 150 config TARGET_SOCFPGA_AGILEX5_SOCDK
 151         bool "Intel SOCFPGA SoCDK (Agilex5)"
 152         select TARGET_SOCFPGA_AGILEX5
 153
 154 config TARGET_SOCFPGA_ARIES_MCVEVK
 155         bool "Aries MCVEVK (Cyclone V)"
 156         select TARGET_SOCFPGA_CYCLONE5
 157
 158 config TARGET_SOCFPGA_ARRIA10_SOCDK
 159         bool "Altera SOCFPGA SoCDK (Arria 10)"
 160         select TARGET_SOCFPGA_ARRIA10
 161
 162 config TARGET_SOCFPGA_ARRIA5_SECU1
 163         bool "ABB SECU1 (Arria V)"
 164         select TARGET_SOCFPGA_ARRIA5
 165         select VENDOR_KM
 166
 167 config TARGET_SOCFPGA_ARRIA5_SOCDK
 168         bool "Altera SOCFPGA SoCDK (Arria V)"
 169         select TARGET_SOCFPGA_ARRIA5
 170
 171 config TARGET_SOCFPGA_CHAMELEONV3
 172         bool "Google Chameleon v3 (Arria 10)"
 173         select TARGET_SOCFPGA_ARRIA10
 174
 175 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 176         bool "Altera SOCFPGA SoCDK (Cyclone V)"
 177         select TARGET_SOCFPGA_CYCLONE5
 178
 179 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 180         bool "Devboards DBM-SoC1 (Cyclone V)"
 181         select TARGET_SOCFPGA_CYCLONE5
 182
 183 config TARGET_SOCFPGA_EBV_SOCRATES
 184         bool "EBV SoCrates (Cyclone V)"
 185         select TARGET_SOCFPGA_CYCLONE5
 186
 187 config TARGET_SOCFPGA_IS1
 188         bool "IS1 (Cyclone V)"
 189         select TARGET_SOCFPGA_CYCLONE5
 190
 191 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 192         bool "Softing VIN|ING FPGA (Cyclone V)"
 193         select BOARD_LATE_INIT
 194         select TARGET_SOCFPGA_CYCLONE5
 195
 196 config TARGET_SOCFPGA_SR1500
 197         bool "SR1500 (Cyclone V)"
 198         select TARGET_SOCFPGA_CYCLONE5
 199
 200 config TARGET_SOCFPGA_STRATIX10_SOCDK
 201         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 202         select TARGET_SOCFPGA_STRATIX10
 203
 204 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 205         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 206         select TARGET_SOCFPGA_CYCLONE5
 207
 208 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 209         bool "Terasic DE10-Nano (Cyclone V)"
 210         select TARGET_SOCFPGA_CYCLONE5
 211
 212 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 213         bool "Terasic DE10-Standard (Cyclone V)"
 214         select TARGET_SOCFPGA_CYCLONE5
 215
 216 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 217         bool "Terasic DE1-SoC (Cyclone V)"
 218         select TARGET_SOCFPGA_CYCLONE5
 219
 220 config TARGET_SOCFPGA_TERASIC_SOCKIT
 221         bool "Terasic SoCkit (Cyclone V)"
 222         select TARGET_SOCFPGA_CYCLONE5
 223
 224 endchoice
 225
 226 config SYS_BOARD
 227         default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
 228         default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 229         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 230         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 231         default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
 232         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 233         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 234         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 235         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 236         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 237         default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 238         default "is1" if TARGET_SOCFPGA_IS1
 239         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 240         default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
 241         default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 242         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 243         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 244         default "sr1500" if TARGET_SOCFPGA_SR1500
 245         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 246         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 247
 248 config SYS_VENDOR
 249         default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
 250         default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 251         default "intel" if TARGET_SOCFPGA_N5X_SOCDK
 252         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 253         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 254         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 255         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 256         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 257         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 258         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 259         default "google" if TARGET_SOCFPGA_CHAMELEONV3
 260         default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 261         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 262         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 263         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 264         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 265         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 266         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 267
 268 config SYS_SOC
 269         default "socfpga"
 270
 271 config SYS_CONFIG_NAME
 272         default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
 273         default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 274         default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 275         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 276         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 277         default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
 278         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 279         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 280         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 281         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 282         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 283         default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
 284         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 285         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 286         default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
 287         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 288         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 289         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 290         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 291         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 292
 293 endif