arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SPL_SIZE_LIMIT
  10         default 0x10000 if TARGET_SOCFPGA_GEN5
  11
  12 config SPL_SIZE_LIMIT_PROVIDE_STACK
  13         default 0x200 if TARGET_SOCFPGA_GEN5
  14
  15 config SPL_STACK_R_ADDR
  16         default 0x00800000 if TARGET_SOCFPGA_GEN5
  17
  18 config SPL_SYS_MALLOC_F_LEN
  19         default 0x800 if TARGET_SOCFPGA_GEN5
  20
  21 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  22         default 0xa2
  23
  24 config SYS_MALLOC_F_LEN
  25         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  26         default 0x2000 if TARGET_SOCFPGA_GEN5
  27
  28 config SYS_TEXT_BASE
  29         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  30         default 0x01000040 if TARGET_SOCFPGA_GEN5
  31
  32 config TARGET_SOCFPGA_AGILEX
  33         bool
  34         select ARMV8_MULTIENTRY
  35         select ARMV8_SET_SMPEN
  36         select ARMV8_SPIN_TABLE
  37         select CLK
  38         select FPGA_INTEL_SDM_MAILBOX
  39         select NCORE_CACHE
  40         select SPL_CLK if SPL
  41
  42 config TARGET_SOCFPGA_ARRIA5
  43         bool
  44         select TARGET_SOCFPGA_GEN5
  45
  46 config TARGET_SOCFPGA_ARRIA10
  47         bool
  48         select SPL_ALTERA_SDRAM
  49         select SPL_BOARD_INIT if SPL
  50         select SPL_CACHE if SPL
  51         select CLK
  52         select SPL_CLK if SPL
  53         select DM_I2C
  54         select DM_RESET
  55         select SPL_DM_RESET if SPL
  56         select REGMAP
  57         select SPL_REGMAP if SPL
  58         select SYSCON
  59         select SPL_SYSCON if SPL
  60         select ETH_DESIGNWARE_SOCFPGA
  61         imply FPGA_SOCFPGA
  62         imply SPL_USE_TINY_PRINTF
  63
  64 config TARGET_SOCFPGA_CYCLONE5
  65         bool
  66         select TARGET_SOCFPGA_GEN5
  67
  68 config TARGET_SOCFPGA_GEN5
  69         bool
  70         select SPL_ALTERA_SDRAM
  71         imply FPGA_SOCFPGA
  72         imply SPL_SIZE_LIMIT_SUBTRACT_GD
  73         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  74         imply SPL_STACK_R
  75         imply SPL_SYS_MALLOC_SIMPLE
  76         imply SPL_USE_TINY_PRINTF
  77
  78 config TARGET_SOCFPGA_STRATIX10
  79         bool
  80         select ARMV8_MULTIENTRY
  81         select ARMV8_SET_SMPEN
  82         select ARMV8_SPIN_TABLE
  83         select FPGA_INTEL_SDM_MAILBOX
  84
  85 choice
  86         prompt "Altera SOCFPGA board select"
  87         optional
  88
  89 config TARGET_SOCFPGA_AGILEX_SOCDK
  90         bool "Intel SOCFPGA SoCDK (Agilex)"
  91         select TARGET_SOCFPGA_AGILEX
  92
  93 config TARGET_SOCFPGA_ARIES_MCVEVK
  94         bool "Aries MCVEVK (Cyclone V)"
  95         select TARGET_SOCFPGA_CYCLONE5
  96
  97 config TARGET_SOCFPGA_ARRIA10_SOCDK
  98         bool "Altera SOCFPGA SoCDK (Arria 10)"
  99         select TARGET_SOCFPGA_ARRIA10
 100
 101 config TARGET_SOCFPGA_ARRIA5_SECU1
 102         bool "ABB SECU1 (Arria V)"
 103         select TARGET_SOCFPGA_ARRIA5
 104         select VENDOR_KM
 105
 106 config TARGET_SOCFPGA_ARRIA5_SOCDK
 107         bool "Altera SOCFPGA SoCDK (Arria V)"
 108         select TARGET_SOCFPGA_ARRIA5
 109
 110 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 111         bool "Altera SOCFPGA SoCDK (Cyclone V)"
 112         select TARGET_SOCFPGA_CYCLONE5
 113
 114 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 115         bool "Devboards DBM-SoC1 (Cyclone V)"
 116         select TARGET_SOCFPGA_CYCLONE5
 117
 118 config TARGET_SOCFPGA_EBV_SOCRATES
 119         bool "EBV SoCrates (Cyclone V)"
 120         select TARGET_SOCFPGA_CYCLONE5
 121
 122 config TARGET_SOCFPGA_IS1
 123         bool "IS1 (Cyclone V)"
 124         select TARGET_SOCFPGA_CYCLONE5
 125
 126 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 127         bool "Softing VIN|ING FPGA (Cyclone V)"
 128         select BOARD_LATE_INIT
 129         select TARGET_SOCFPGA_CYCLONE5
 130
 131 config TARGET_SOCFPGA_SR1500
 132         bool "SR1500 (Cyclone V)"
 133         select TARGET_SOCFPGA_CYCLONE5
 134
 135 config TARGET_SOCFPGA_STRATIX10_SOCDK
 136         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 137         select TARGET_SOCFPGA_STRATIX10
 138
 139 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 140         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 141         select TARGET_SOCFPGA_CYCLONE5
 142
 143 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 144         bool "Terasic DE10-Nano (Cyclone V)"
 145         select TARGET_SOCFPGA_CYCLONE5
 146
 147 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 148         bool "Terasic DE1-SoC (Cyclone V)"
 149         select TARGET_SOCFPGA_CYCLONE5
 150
 151 config TARGET_SOCFPGA_TERASIC_SOCKIT
 152         bool "Terasic SoCkit (Cyclone V)"
 153         select TARGET_SOCFPGA_CYCLONE5
 154
 155 endchoice
 156
 157 config SYS_BOARD
 158         default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 159         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 160         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 161         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 162         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 163         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 164         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 165         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 166         default "is1" if TARGET_SOCFPGA_IS1
 167         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 168         default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 169         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 170         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 171         default "sr1500" if TARGET_SOCFPGA_SR1500
 172         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 173         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 174
 175 config SYS_VENDOR
 176         default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 177         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 178         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 179         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 180         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 181         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 182         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 183         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 184         default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 185         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 186         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 187         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 188         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 189         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 190
 191 config SYS_SOC
 192         default "socfpga"
 193
 194 config SYS_CONFIG_NAME
 195         default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 196         default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 197         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 198         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 199         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 200         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 201         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 202         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 203         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 204         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 205         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 206         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 207         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 208         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 209         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 210         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 211
 212 source "board/keymile/Kconfig"
 213
 214 endif