arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
   4         default 0xa2
   5
   6 config TARGET_SOCFPGA_ARRIA5
   7         bool
   8         select TARGET_SOCFPGA_GEN5
   9
  10 config TARGET_SOCFPGA_ARRIA10
  11         bool
  12         select ALTERA_SDRAM
  13         select SPL_BOARD_INIT if SPL
  14         select CLK
  15         select SPL_CLK if SPL
  16         select DM_I2C
  17         select DM_RESET
  18         select SPL_DM_RESET if SPL
  19         select REGMAP
  20         select SPL_REGMAP if SPL
  21         select SYSCON
  22         select SPL_SYSCON if SPL
  23         select ETH_DESIGNWARE_SOCFPGA
  24
  25 config TARGET_SOCFPGA_CYCLONE5
  26         bool
  27         select TARGET_SOCFPGA_GEN5
  28
  29 config TARGET_SOCFPGA_GEN5
  30         bool
  31         select ALTERA_SDRAM
  32
  33 config TARGET_SOCFPGA_STRATIX10
  34         bool
  35         select ARMV8_MULTIENTRY
  36         select ARMV8_SET_SMPEN
  37         select ARMV8_SPIN_TABLE
  38
  39 choice
  40         prompt "Altera SOCFPGA board select"
  41         optional
  42
  43 config TARGET_SOCFPGA_ARRIA10_SOCDK
  44         bool "Altera SOCFPGA SoCDK (Arria 10)"
  45         select TARGET_SOCFPGA_ARRIA10
  46
  47 config TARGET_SOCFPGA_ARRIA5_SOCDK
  48         bool "Altera SOCFPGA SoCDK (Arria V)"
  49         select TARGET_SOCFPGA_ARRIA5
  50
  51 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  52         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  53         select TARGET_SOCFPGA_CYCLONE5
  54
  55 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  56         bool "Devboards DBM-SoC1 (Cyclone V)"
  57         select TARGET_SOCFPGA_CYCLONE5
  58
  59 config TARGET_SOCFPGA_EBV_SOCRATES
  60         bool "EBV SoCrates (Cyclone V)"
  61         select TARGET_SOCFPGA_CYCLONE5
  62
  63 config TARGET_SOCFPGA_IS1
  64         bool "IS1 (Cyclone V)"
  65         select TARGET_SOCFPGA_CYCLONE5
  66
  67 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  68         bool "samtec VIN|ING FPGA (Cyclone V)"
  69         select BOARD_LATE_INIT
  70         select TARGET_SOCFPGA_CYCLONE5
  71
  72 config TARGET_SOCFPGA_SR1500
  73         bool "SR1500 (Cyclone V)"
  74         select TARGET_SOCFPGA_CYCLONE5
  75
  76 config TARGET_SOCFPGA_STRATIX10_SOCDK
  77         bool "Intel SOCFPGA SoCDK (Stratix 10)"
  78         select TARGET_SOCFPGA_STRATIX10
  79
  80 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  81         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  82         select TARGET_SOCFPGA_CYCLONE5
  83
  84 config TARGET_SOCFPGA_TERASIC_DE10_NANO
  85         bool "Terasic DE10-Nano (Cyclone V)"
  86         select TARGET_SOCFPGA_CYCLONE5
  87
  88 config TARGET_SOCFPGA_TERASIC_DE1_SOC
  89         bool "Terasic DE1-SoC (Cyclone V)"
  90         select TARGET_SOCFPGA_CYCLONE5
  91
  92 config TARGET_SOCFPGA_TERASIC_SOCKIT
  93         bool "Terasic SoCkit (Cyclone V)"
  94         select TARGET_SOCFPGA_CYCLONE5
  95
  96 endchoice
  97
  98 config SYS_BOARD
  99         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 100         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 101         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 102         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 103         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 104         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 105         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 106         default "is1" if TARGET_SOCFPGA_IS1
 107         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 108         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 109         default "sr1500" if TARGET_SOCFPGA_SR1500
 110         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 111         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 112
 113 config SYS_VENDOR
 114         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 115         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 116         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 117         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 118         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 119         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 120         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 121         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 122         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 123         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 124         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 125
 126 config SYS_SOC
 127         default "socfpga"
 128
 129 config SYS_CONFIG_NAME
 130         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 131         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 132         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 133         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 134         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 135         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 136         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 137         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 138         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 139         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 140         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 141         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 142         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 143
 144 endif