arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SPL_LIBCOMMON_SUPPORT
   4         default y
   5
   6 config SPL_LIBDISK_SUPPORT
   7         default y
   8
   9 config SPL_LIBGENERIC_SUPPORT
  10         default y
  11
  12 config SPL_MMC_SUPPORT
  13         default y if DM_MMC
  14
  15 config SPL_NAND_SUPPORT
  16         default y if SPL_NAND_DENALI
  17
  18 config SPL_SERIAL_SUPPORT
  19         default y
  20
  21 config SPL_SPI_FLASH_SUPPORT
  22         default y if SPL_SPI_SUPPORT
  23
  24 config SPL_SPI_SUPPORT
  25         default y if DM_SPI
  26
  27 config SPL_WATCHDOG_SUPPORT
  28         default y
  29
  30 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
  31         default y
  32
  33 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  34         default 0xa2
  35
  36 config TARGET_SOCFPGA_ARRIA5
  37         bool
  38         select TARGET_SOCFPGA_GEN5
  39
  40 config TARGET_SOCFPGA_ARRIA10
  41         bool
  42         select SPL_BOARD_INIT if SPL
  43
  44 config TARGET_SOCFPGA_CYCLONE5
  45         bool
  46         select TARGET_SOCFPGA_GEN5
  47
  48 config TARGET_SOCFPGA_GEN5
  49         bool
  50         select ALTERA_SDRAM
  51
  52 choice
  53         prompt "Altera SOCFPGA board select"
  54         optional
  55
  56 config TARGET_SOCFPGA_ARRIA10_SOCDK
  57         bool "Altera SOCFPGA SoCDK (Arria 10)"
  58         select TARGET_SOCFPGA_ARRIA10
  59
  60 config TARGET_SOCFPGA_ARRIA5_SOCDK
  61         bool "Altera SOCFPGA SoCDK (Arria V)"
  62         select TARGET_SOCFPGA_ARRIA5
  63
  64 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  65         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  66         select TARGET_SOCFPGA_CYCLONE5
  67
  68 config TARGET_SOCFPGA_ARIES_MCVEVK
  69         bool "Aries MCVEVK (Cyclone V)"
  70         select TARGET_SOCFPGA_CYCLONE5
  71
  72 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  73         bool "Devboards DBM-SoC1 (Cyclone V)"
  74         select TARGET_SOCFPGA_CYCLONE5
  75
  76 config TARGET_SOCFPGA_EBV_SOCRATES
  77         bool "EBV SoCrates (Cyclone V)"
  78         select TARGET_SOCFPGA_CYCLONE5
  79
  80 config TARGET_SOCFPGA_IS1
  81         bool "IS1 (Cyclone V)"
  82         select TARGET_SOCFPGA_CYCLONE5
  83
  84 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  85         bool "samtec VIN|ING FPGA (Cyclone V)"
  86         select BOARD_LATE_INIT
  87         select TARGET_SOCFPGA_CYCLONE5
  88
  89 config TARGET_SOCFPGA_SR1500
  90         bool "SR1500 (Cyclone V)"
  91         select TARGET_SOCFPGA_CYCLONE5
  92
  93 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  94         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  95         select TARGET_SOCFPGA_CYCLONE5
  96
  97 config TARGET_SOCFPGA_TERASIC_DE10_NANO
  98         bool "Terasic DE10-Nano (Cyclone V)"
  99         select TARGET_SOCFPGA_CYCLONE5
 100
 101 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 102         bool "Terasic DE1-SoC (Cyclone V)"
 103         select TARGET_SOCFPGA_CYCLONE5
 104
 105 config TARGET_SOCFPGA_TERASIC_SOCKIT
 106         bool "Terasic SoCkit (Cyclone V)"
 107         select TARGET_SOCFPGA_CYCLONE5
 108
 109 endchoice
 110
 111 config SYS_BOARD
 112         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 113         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 114         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 115         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 116         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 117         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 118         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 119         default "is1" if TARGET_SOCFPGA_IS1
 120         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 121         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 122         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 123         default "sr1500" if TARGET_SOCFPGA_SR1500
 124         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 125
 126 config SYS_VENDOR
 127         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 128         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 129         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 130         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 131         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 132         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 133         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 134         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 135         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 136         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 137         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 138
 139 config SYS_SOC
 140         default "socfpga"
 141
 142 config SYS_CONFIG_NAME
 143         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 144         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 145         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 146         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 147         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 148         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 149         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 150         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 151         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 152         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 153         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 154         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 155         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 156
 157 endif