4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
9 config SOCFPGA_SECURE_VAB_AUTH
10 bool "Enable boot image authentication with Secure Device Manager"
11 depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
12 select FIT_IMAGE_POST_PROCESS
15 select SPL_FIT_IMAGE_POST_PROCESS
17 All images loaded from FIT will be authenticated by Secure Device
20 config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
21 bool "Allow non-FIT VAB signed images"
22 depends on SOCFPGA_SECURE_VAB_AUTH
25 default 0x10000 if TARGET_SOCFPGA_GEN5
27 config SPL_SIZE_LIMIT_PROVIDE_STACK
28 default 0x200 if TARGET_SOCFPGA_GEN5
30 config SPL_STACK_R_ADDR
31 default 0x00800000 if TARGET_SOCFPGA_GEN5
33 config SPL_SYS_MALLOC_F_LEN
34 default 0x800 if TARGET_SOCFPGA_GEN5
36 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
39 config SYS_MALLOC_F_LEN
40 default 0x2000 if TARGET_SOCFPGA_ARRIA10
41 default 0x2000 if TARGET_SOCFPGA_GEN5
44 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
45 default 0x01000040 if TARGET_SOCFPGA_GEN5
47 config TARGET_SOCFPGA_AGILEX
49 select ARMV8_MULTIENTRY
50 select ARMV8_SET_SMPEN
51 select BINMAN if SPL_ATF
53 select FPGA_INTEL_SDM_MAILBOX
56 select TARGET_SOCFPGA_SOC64
58 config TARGET_SOCFPGA_ARRIA5
60 select TARGET_SOCFPGA_GEN5
62 config TARGET_SOCFPGA_ARRIA10
64 select SPL_ALTERA_SDRAM
65 select SPL_BOARD_INIT if SPL
66 select SPL_CACHE if SPL
71 select SPL_DM_RESET if SPL
73 select SPL_REGMAP if SPL
75 select SPL_SYSCON if SPL
76 select ETH_DESIGNWARE_SOCFPGA
78 imply SPL_USE_TINY_PRINTF
80 config TARGET_SOCFPGA_CYCLONE5
82 select TARGET_SOCFPGA_GEN5
84 config TARGET_SOCFPGA_GEN5
86 select SPL_ALTERA_SDRAM
88 imply SPL_SIZE_LIMIT_SUBTRACT_GD
89 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
91 imply SPL_SYS_MALLOC_SIMPLE
92 imply SPL_USE_TINY_PRINTF
94 config TARGET_SOCFPGA_N5X
96 select ARMV8_MULTIENTRY
97 select ARMV8_SET_SMPEN
98 select BINMAN if SPL_ATF
100 select FPGA_INTEL_SDM_MAILBOX
102 select SPL_ALTERA_SDRAM
103 select SPL_CLK if SPL
104 select TARGET_SOCFPGA_SOC64
106 config TARGET_SOCFPGA_N5X_SOCDK
107 bool "Intel eASIC SoCDK (N5X)"
108 select TARGET_SOCFPGA_N5X
110 config TARGET_SOCFPGA_SOC64
113 config TARGET_SOCFPGA_STRATIX10
115 select ARMV8_MULTIENTRY
116 select ARMV8_SET_SMPEN
117 select BINMAN if SPL_ATF
118 select FPGA_INTEL_SDM_MAILBOX
119 select TARGET_SOCFPGA_SOC64
122 prompt "Altera SOCFPGA board select"
125 config TARGET_SOCFPGA_AGILEX_SOCDK
126 bool "Intel SOCFPGA SoCDK (Agilex)"
127 select TARGET_SOCFPGA_AGILEX
129 config TARGET_SOCFPGA_ARIES_MCVEVK
130 bool "Aries MCVEVK (Cyclone V)"
131 select TARGET_SOCFPGA_CYCLONE5
133 config TARGET_SOCFPGA_ARRIA10_SOCDK
134 bool "Altera SOCFPGA SoCDK (Arria 10)"
135 select TARGET_SOCFPGA_ARRIA10
137 config TARGET_SOCFPGA_ARRIA5_SECU1
138 bool "ABB SECU1 (Arria V)"
139 select TARGET_SOCFPGA_ARRIA5
142 config TARGET_SOCFPGA_ARRIA5_SOCDK
143 bool "Altera SOCFPGA SoCDK (Arria V)"
144 select TARGET_SOCFPGA_ARRIA5
146 config TARGET_SOCFPGA_CHAMELEONV3
147 bool "Google Chameleon v3 (Arria 10)"
148 select TARGET_SOCFPGA_ARRIA10
150 config TARGET_SOCFPGA_CYCLONE5_SOCDK
151 bool "Altera SOCFPGA SoCDK (Cyclone V)"
152 select TARGET_SOCFPGA_CYCLONE5
154 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
155 bool "Devboards DBM-SoC1 (Cyclone V)"
156 select TARGET_SOCFPGA_CYCLONE5
158 config TARGET_SOCFPGA_EBV_SOCRATES
159 bool "EBV SoCrates (Cyclone V)"
160 select TARGET_SOCFPGA_CYCLONE5
162 config TARGET_SOCFPGA_IS1
163 bool "IS1 (Cyclone V)"
164 select TARGET_SOCFPGA_CYCLONE5
166 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
167 bool "Softing VIN|ING FPGA (Cyclone V)"
168 select BOARD_LATE_INIT
169 select TARGET_SOCFPGA_CYCLONE5
171 config TARGET_SOCFPGA_SR1500
172 bool "SR1500 (Cyclone V)"
173 select TARGET_SOCFPGA_CYCLONE5
175 config TARGET_SOCFPGA_STRATIX10_SOCDK
176 bool "Intel SOCFPGA SoCDK (Stratix 10)"
177 select TARGET_SOCFPGA_STRATIX10
179 config TARGET_SOCFPGA_TERASIC_DE0_NANO
180 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
181 select TARGET_SOCFPGA_CYCLONE5
183 config TARGET_SOCFPGA_TERASIC_DE10_NANO
184 bool "Terasic DE10-Nano (Cyclone V)"
185 select TARGET_SOCFPGA_CYCLONE5
187 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
188 bool "Terasic DE10-Standard (Cyclone V)"
189 select TARGET_SOCFPGA_CYCLONE5
191 config TARGET_SOCFPGA_TERASIC_DE1_SOC
192 bool "Terasic DE1-SoC (Cyclone V)"
193 select TARGET_SOCFPGA_CYCLONE5
195 config TARGET_SOCFPGA_TERASIC_SOCKIT
196 bool "Terasic SoCkit (Cyclone V)"
197 select TARGET_SOCFPGA_CYCLONE5
202 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
203 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
204 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
205 default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
206 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
207 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
208 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
209 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
210 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
211 default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
212 default "is1" if TARGET_SOCFPGA_IS1
213 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
214 default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
215 default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
216 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
217 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
218 default "sr1500" if TARGET_SOCFPGA_SR1500
219 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
220 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
223 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
224 default "intel" if TARGET_SOCFPGA_N5X_SOCDK
225 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
226 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
227 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
228 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
229 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
230 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
231 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
232 default "google" if TARGET_SOCFPGA_CHAMELEONV3
233 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
234 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
235 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
236 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
237 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
238 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
239 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
244 config SYS_CONFIG_NAME
245 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
246 default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
247 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
248 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
249 default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
250 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
251 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
252 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
253 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
254 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
255 default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
256 default "socfpga_is1" if TARGET_SOCFPGA_IS1
257 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
258 default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
259 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
260 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
261 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
262 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
263 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA