arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config NR_DRAM_BANKS
   4         default 1
   5
   6 config SPL_STACK_R_ADDR
   7         default 0x00800000 if TARGET_SOCFPGA_GEN5
   8
   9 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  10         default 0xa2
  11
  12 config SYS_MALLOC_F_LEN
  13         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  14         default 0x2000 if TARGET_SOCFPGA_GEN5
  15
  16 config SYS_TEXT_BASE
  17         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  18         default 0x01000040 if TARGET_SOCFPGA_GEN5
  19
  20 config TARGET_SOCFPGA_ARRIA5
  21         bool
  22         select TARGET_SOCFPGA_GEN5
  23
  24 config TARGET_SOCFPGA_ARRIA10
  25         bool
  26         select ALTERA_SDRAM
  27         select SPL_BOARD_INIT if SPL
  28         select CLK
  29         select SPL_CLK if SPL
  30         select DM_I2C
  31         select DM_RESET
  32         select SPL_DM_RESET if SPL
  33         select REGMAP
  34         select SPL_REGMAP if SPL
  35         select SYSCON
  36         select SPL_SYSCON if SPL
  37         select ETH_DESIGNWARE_SOCFPGA
  38         imply FPGA_SOCFPGA
  39         imply USE_TINY_PRINTF
  40
  41 config TARGET_SOCFPGA_CYCLONE5
  42         bool
  43         select TARGET_SOCFPGA_GEN5
  44
  45 config TARGET_SOCFPGA_GEN5
  46         bool
  47         select ALTERA_SDRAM
  48         imply FPGA_SOCFPGA
  49         imply SPL_STACK_R
  50         imply SPL_SYS_MALLOC_SIMPLE
  51         imply USE_TINY_PRINTF
  52
  53 config TARGET_SOCFPGA_STRATIX10
  54         bool
  55         select ARMV8_MULTIENTRY
  56         select ARMV8_SET_SMPEN
  57         select ARMV8_SPIN_TABLE
  58         select FPGA_STRATIX10
  59
  60 choice
  61         prompt "Altera SOCFPGA board select"
  62         optional
  63
  64 config TARGET_SOCFPGA_ARRIA10_SOCDK
  65         bool "Altera SOCFPGA SoCDK (Arria 10)"
  66         select TARGET_SOCFPGA_ARRIA10
  67
  68 config TARGET_SOCFPGA_ARRIA5_SOCDK
  69         bool "Altera SOCFPGA SoCDK (Arria V)"
  70         select TARGET_SOCFPGA_ARRIA5
  71
  72 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  73         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  74         select TARGET_SOCFPGA_CYCLONE5
  75
  76 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
  77         bool "Devboards DBM-SoC1 (Cyclone V)"
  78         select TARGET_SOCFPGA_CYCLONE5
  79
  80 config TARGET_SOCFPGA_EBV_SOCRATES
  81         bool "EBV SoCrates (Cyclone V)"
  82         select TARGET_SOCFPGA_CYCLONE5
  83
  84 config TARGET_SOCFPGA_IS1
  85         bool "IS1 (Cyclone V)"
  86         select TARGET_SOCFPGA_CYCLONE5
  87
  88 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  89         bool "samtec VIN|ING FPGA (Cyclone V)"
  90         select BOARD_LATE_INIT
  91         select TARGET_SOCFPGA_CYCLONE5
  92
  93 config TARGET_SOCFPGA_SR1500
  94         bool "SR1500 (Cyclone V)"
  95         select TARGET_SOCFPGA_CYCLONE5
  96
  97 config TARGET_SOCFPGA_STRATIX10_SOCDK
  98         bool "Intel SOCFPGA SoCDK (Stratix 10)"
  99         select TARGET_SOCFPGA_STRATIX10
 100
 101 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 102         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 103         select TARGET_SOCFPGA_CYCLONE5
 104
 105 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 106         bool "Terasic DE10-Nano (Cyclone V)"
 107         select TARGET_SOCFPGA_CYCLONE5
 108
 109 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 110         bool "Terasic DE1-SoC (Cyclone V)"
 111         select TARGET_SOCFPGA_CYCLONE5
 112
 113 config TARGET_SOCFPGA_TERASIC_SOCKIT
 114         bool "Terasic SoCkit (Cyclone V)"
 115         select TARGET_SOCFPGA_CYCLONE5
 116
 117 endchoice
 118
 119 config SYS_BOARD
 120         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 121         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 122         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 123         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 124         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 125         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 126         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 127         default "is1" if TARGET_SOCFPGA_IS1
 128         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 129         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 130         default "sr1500" if TARGET_SOCFPGA_SR1500
 131         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 132         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 133
 134 config SYS_VENDOR
 135         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 136         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 137         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 138         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 139         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 140         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 141         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 142         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 143         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 144         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 145         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 146
 147 config SYS_SOC
 148         default "socfpga"
 149
 150 config SYS_CONFIG_NAME
 151         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 152         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 153         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 154         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 155         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 156         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 157         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 158         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 159         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 160         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 161         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 162         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 163         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 164
 165 endif