arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config ERR_PTR_OFFSET
   4         default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
   5
   6 config NR_DRAM_BANKS
   7         default 1
   8
   9 config SOCFPGA_SECURE_VAB_AUTH
  10         bool "Enable boot image authentication with Secure Device Manager"
  11         depends on TARGET_SOCFPGA_AGILEX
  12         select FIT_IMAGE_POST_PROCESS
  13         select SHA384
  14         select SHA512_ALGO
  15         select SPL_FIT_IMAGE_POST_PROCESS
  16         help
  17          All images loaded from FIT will be authenticated by Secure Device
  18          Manager.
  19
  20 config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
  21         bool "Allow non-FIT VAB signed images"
  22         depends on SOCFPGA_SECURE_VAB_AUTH
  23
  24 config SPL_SIZE_LIMIT
  25         default 0x10000 if TARGET_SOCFPGA_GEN5
  26
  27 config SPL_SIZE_LIMIT_PROVIDE_STACK
  28         default 0x200 if TARGET_SOCFPGA_GEN5
  29
  30 config SPL_STACK_R_ADDR
  31         default 0x00800000 if TARGET_SOCFPGA_GEN5
  32
  33 config SPL_SYS_MALLOC_F_LEN
  34         default 0x800 if TARGET_SOCFPGA_GEN5
  35
  36 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
  37         default 0xa2
  38
  39 config SYS_MALLOC_F_LEN
  40         default 0x2000 if TARGET_SOCFPGA_ARRIA10
  41         default 0x2000 if TARGET_SOCFPGA_GEN5
  42
  43 config SYS_TEXT_BASE
  44         default 0x01000040 if TARGET_SOCFPGA_ARRIA10
  45         default 0x01000040 if TARGET_SOCFPGA_GEN5
  46
  47 config TARGET_SOCFPGA_AGILEX
  48         bool
  49         select ARMV8_MULTIENTRY
  50         select ARMV8_SET_SMPEN
  51         select BINMAN if SPL_ATF
  52         select CLK
  53         select FPGA_INTEL_SDM_MAILBOX
  54         select NCORE_CACHE
  55         select SPL_CLK if SPL
  56         select TARGET_SOCFPGA_SOC64
  57
  58 config TARGET_SOCFPGA_ARRIA5
  59         bool
  60         select TARGET_SOCFPGA_GEN5
  61
  62 config TARGET_SOCFPGA_ARRIA10
  63         bool
  64         select SPL_ALTERA_SDRAM
  65         select SPL_BOARD_INIT if SPL
  66         select SPL_CACHE if SPL
  67         select CLK
  68         select SPL_CLK if SPL
  69         select DM_I2C
  70         select DM_RESET
  71         select SPL_DM_RESET if SPL
  72         select REGMAP
  73         select SPL_REGMAP if SPL
  74         select SYSCON
  75         select SPL_SYSCON if SPL
  76         select ETH_DESIGNWARE_SOCFPGA
  77         imply FPGA_SOCFPGA
  78         imply SPL_USE_TINY_PRINTF
  79
  80 config TARGET_SOCFPGA_CYCLONE5
  81         bool
  82         select TARGET_SOCFPGA_GEN5
  83
  84 config TARGET_SOCFPGA_GEN5
  85         bool
  86         select SPL_ALTERA_SDRAM
  87         imply FPGA_SOCFPGA
  88         imply SPL_SIZE_LIMIT_SUBTRACT_GD
  89         imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
  90         imply SPL_STACK_R
  91         imply SPL_SYS_MALLOC_SIMPLE
  92         imply SPL_USE_TINY_PRINTF
  93
  94 config TARGET_SOCFPGA_SOC64
  95         bool
  96
  97 config TARGET_SOCFPGA_STRATIX10
  98         bool
  99         select ARMV8_MULTIENTRY
 100         select ARMV8_SET_SMPEN
 101         select BINMAN if SPL_ATF
 102         select FPGA_INTEL_SDM_MAILBOX
 103         select TARGET_SOCFPGA_SOC64
 104
 105 choice
 106         prompt "Altera SOCFPGA board select"
 107         optional
 108
 109 config TARGET_SOCFPGA_AGILEX_SOCDK
 110         bool "Intel SOCFPGA SoCDK (Agilex)"
 111         select TARGET_SOCFPGA_AGILEX
 112
 113 config TARGET_SOCFPGA_ARIES_MCVEVK
 114         bool "Aries MCVEVK (Cyclone V)"
 115         select TARGET_SOCFPGA_CYCLONE5
 116
 117 config TARGET_SOCFPGA_ARRIA10_SOCDK
 118         bool "Altera SOCFPGA SoCDK (Arria 10)"
 119         select TARGET_SOCFPGA_ARRIA10
 120
 121 config TARGET_SOCFPGA_ARRIA5_SECU1
 122         bool "ABB SECU1 (Arria V)"
 123         select TARGET_SOCFPGA_ARRIA5
 124         select VENDOR_KM
 125
 126 config TARGET_SOCFPGA_ARRIA5_SOCDK
 127         bool "Altera SOCFPGA SoCDK (Arria V)"
 128         select TARGET_SOCFPGA_ARRIA5
 129
 130 config TARGET_SOCFPGA_CYCLONE5_SOCDK
 131         bool "Altera SOCFPGA SoCDK (Cyclone V)"
 132         select TARGET_SOCFPGA_CYCLONE5
 133
 134 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 135         bool "Devboards DBM-SoC1 (Cyclone V)"
 136         select TARGET_SOCFPGA_CYCLONE5
 137
 138 config TARGET_SOCFPGA_EBV_SOCRATES
 139         bool "EBV SoCrates (Cyclone V)"
 140         select TARGET_SOCFPGA_CYCLONE5
 141
 142 config TARGET_SOCFPGA_IS1
 143         bool "IS1 (Cyclone V)"
 144         select TARGET_SOCFPGA_CYCLONE5
 145
 146 config TARGET_SOCFPGA_SOFTING_VINING_FPGA
 147         bool "Softing VIN|ING FPGA (Cyclone V)"
 148         select BOARD_LATE_INIT
 149         select TARGET_SOCFPGA_CYCLONE5
 150
 151 config TARGET_SOCFPGA_SR1500
 152         bool "SR1500 (Cyclone V)"
 153         select TARGET_SOCFPGA_CYCLONE5
 154
 155 config TARGET_SOCFPGA_STRATIX10_SOCDK
 156         bool "Intel SOCFPGA SoCDK (Stratix 10)"
 157         select TARGET_SOCFPGA_STRATIX10
 158
 159 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 160         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 161         select TARGET_SOCFPGA_CYCLONE5
 162
 163 config TARGET_SOCFPGA_TERASIC_DE10_NANO
 164         bool "Terasic DE10-Nano (Cyclone V)"
 165         select TARGET_SOCFPGA_CYCLONE5
 166
 167 config TARGET_SOCFPGA_TERASIC_DE1_SOC
 168         bool "Terasic DE1-SoC (Cyclone V)"
 169         select TARGET_SOCFPGA_CYCLONE5
 170
 171 config TARGET_SOCFPGA_TERASIC_SOCKIT
 172         bool "Terasic SoCkit (Cyclone V)"
 173         select TARGET_SOCFPGA_CYCLONE5
 174
 175 endchoice
 176
 177 config SYS_BOARD
 178         default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 179         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 180         default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 181         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 182         default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 183         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 184         default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 185         default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 186         default "is1" if TARGET_SOCFPGA_IS1
 187         default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 188         default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 189         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 190         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 191         default "sr1500" if TARGET_SOCFPGA_SR1500
 192         default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 193         default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 194
 195 config SYS_VENDOR
 196         default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 197         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 198         default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 199         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 200         default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
 201         default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 202         default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 203         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
 204         default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 205         default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 206         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 207         default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 208         default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 209         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 210
 211 config SYS_SOC
 212         default "socfpga"
 213
 214 config SYS_CONFIG_NAME
 215         default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 216         default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 217         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 218         default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 219         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 220         default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 221         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 222         default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 223         default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 224         default "socfpga_is1" if TARGET_SOCFPGA_IS1
 225         default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 226         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 227         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 228         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 229         default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
 230         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 231
 232 source "board/keymile/Kconfig"
 233
 234 endif