arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Qualcomm QCS404 sysmap
   4  *
   5  * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
   6  */
   7 #ifndef _MACH_SYSMAP_QCS404_H
   8 #define _MACH_SYSMAP_QCS404_H
   9
  10 #define GICD_BASE                       (0x0b000000)
  11 #define GICC_BASE                       (0x0b002000)
  12
  13 /* Clocks: (from CLK_CTL_BASE)  */
  14 #define GPLL0_STATUS                    (0x21000)
  15 #define GPLL1_STATUS                    (0x20000)
  16 #define APCS_GPLL_ENA_VOTE              (0x45000)
  17 #define APCS_CLOCK_BRANCH_ENA_VOTE      (0x45004)
  18
  19 /* BLSP1 AHB clock (root clock for BLSP) */
  20 #define BLSP1_AHB_CBCR                  0x1008
  21
  22 /* Uart clock control registers */
  23 #define BLSP1_UART2_BCR                 (0x3028)
  24 #define BLSP1_UART2_APPS_CBCR           (0x302C)
  25 #define BLSP1_UART2_APPS_CMD_RCGR       (0x3034)
  26 #define BLSP1_UART2_APPS_CFG_RCGR       (0x3038)
  27 #define BLSP1_UART2_APPS_M              (0x303C)
  28 #define BLSP1_UART2_APPS_N              (0x3040)
  29 #define BLSP1_UART2_APPS_D              (0x3044)
  30
  31 /* SD controller clock control registers */
  32 #define SDCC_BCR(n)                     (((n) * 0x1000) + 0x41000)
  33 #define SDCC_CMD_RCGR(n)                (((n) * 0x1000) + 0x41004)
  34 #define SDCC_CFG_RCGR(n)                (((n) * 0x1000) + 0x41008)
  35 #define SDCC_M(n)                       (((n) * 0x1000) + 0x4100C)
  36 #define SDCC_N(n)                       (((n) * 0x1000) + 0x41010)
  37 #define SDCC_D(n)                       (((n) * 0x1000) + 0x41014)
  38 #define SDCC_APPS_CBCR(n)               (((n) * 0x1000) + 0x41018)
  39 #define SDCC_AHB_CBCR(n)                (((n) * 0x1000) + 0x4101C)
  40
  41 /* USB-3.0 controller clock control registers */
  42 #define SYS_NOC_USB3_CBCR               (0x26014)
  43 #define USB30_BCR                       (0x39000)
  44 #define USB3PHY_BCR                     (0x39008)
  45 #define USB30_MASTER_CBCR               (0x3900C)
  46 #define USB30_SLEEP_CBCR                (0x39010)
  47 #define USB30_MOCK_UTMI_CBCR            (0x39014)
  48 #define USB30_MOCK_UTMI_CMD_RCGR        (0x3901C)
  49 #define USB30_MOCK_UTMI_CFG_RCGR        (0x39020)
  50 #define USB30_MASTER_CMD_RCGR           (0x39028)
  51 #define USB30_MASTER_CFG_RCGR           (0x3902C)
  52 #define USB30_MASTER_M                  (0x39030)
  53 #define USB30_MASTER_N                  (0x39034)
  54 #define USB30_MASTER_D                  (0x39038)
  55 #define USB2A_PHY_SLEEP_CBCR            (0x4102C)
  56 #define USB_HS_PHY_CFG_AHB_CBCR         (0x41030)
  57
  58 /* ETH controller clock control registers */
  59 #define ETH_PTP_CBCR                    (0x4e004)
  60 #define ETH_RGMII_CBCR                  (0x4e008)
  61 #define ETH_SLAVE_AHB_CBCR              (0x4e00c)
  62 #define ETH_AXI_CBCR                    (0x4e010)
  63 #define EMAC_PTP_CMD_RCGR               (0x4e014)
  64 #define EMAC_PTP_CFG_RCGR               (0x4e018)
  65 #define EMAC_CMD_RCGR                   (0x4e01c)
  66 #define EMAC_CFG_RCGR                   (0x4e020)
  67 #define EMAC_M                          (0x4e024)
  68 #define EMAC_N                          (0x4e028)
  69 #define EMAC_D                          (0x4e02c)
  70
  71 #endif