arch/arm/mach-snapdragon/clock-qcs404.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Clock drivers for Qualcomm QCS404
   4  *
   5  * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <asm/io.h>
  13 #include <linux/bitops.h>
  14 #include "clock-snapdragon.h"
  15
  16 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
  17
  18 /* GPLL0 clock control registers */
  19 #define GPLL0_STATUS_ACTIVE BIT(31)
  20
  21 static struct vote_clk gcc_blsp1_ahb_clk = {
  22         .cbcr_reg = BLSP1_AHB_CBCR,
  23         .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
  24         .vote_bit = BIT(10) | BIT(5) | BIT(4),
  25 };
  26
  27 static const struct bcr_regs uart2_regs = {
  28         .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
  29         .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
  30         .M = BLSP1_UART2_APPS_M,
  31         .N = BLSP1_UART2_APPS_N,
  32         .D = BLSP1_UART2_APPS_D,
  33 };
  34
  35 static const struct bcr_regs sdc_regs = {
  36         .cfg_rcgr = SDCC_CFG_RCGR(1),
  37         .cmd_rcgr = SDCC_CMD_RCGR(1),
  38         .M = SDCC_M(1),
  39         .N = SDCC_N(1),
  40         .D = SDCC_D(1),
  41 };
  42
  43 static struct pll_vote_clk gpll0_vote_clk = {
  44         .status = GPLL0_STATUS,
  45         .status_bit = GPLL0_STATUS_ACTIVE,
  46         .ena_vote = APCS_GPLL_ENA_VOTE,
  47         .vote_bit = BIT(0),
  48 };
  49
  50 ulong msm_set_rate(struct clk *clk, ulong rate)
  51 {
  52         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  53
  54         switch (clk->id) {
  55         case GCC_BLSP1_UART2_APPS_CLK:
  56                 /* UART: 115200 */
  57                 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
  58                                      CFG_CLK_SRC_CXO);
  59                 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
  60                 break;
  61         case GCC_BLSP1_AHB_CLK:
  62                 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
  63                 break;
  64         case GCC_SDCC1_APPS_CLK:
  65                 /* SDCC1: 200MHz */
  66                 clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
  67                                      CFG_CLK_SRC_GPLL0);
  68                 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
  69                 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
  70                 break;
  71         case GCC_SDCC1_AHB_CLK:
  72                 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
  73                 break;
  74         default:
  75                 return 0;
  76         }
  77
  78         return 0;
  79 }
  80
  81 int msm_enable(struct clk *clk)
  82 {
  83         return 0;
  84 }