arch/arm/mach-snapdragon/clock-qcs404.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Clock drivers for Qualcomm QCS404
   4  *
   5  * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
   6  */
   7
   8 #include <common.h>
   9 #include <clk-uclass.h>
  10 #include <dm.h>
  11 #include <errno.h>
  12 #include <asm/io.h>
  13 #include <linux/bitops.h>
  14 #include "clock-snapdragon.h"
  15
  16 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
  17
  18 /* GPLL0 clock control registers */
  19 #define GPLL0_STATUS_ACTIVE BIT(31)
  20
  21 static struct vote_clk gcc_blsp1_ahb_clk = {
  22         .cbcr_reg = BLSP1_AHB_CBCR,
  23         .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
  24         .vote_bit = BIT(10) | BIT(5) | BIT(4),
  25 };
  26
  27 static const struct bcr_regs uart2_regs = {
  28         .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
  29         .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
  30         .M = BLSP1_UART2_APPS_M,
  31         .N = BLSP1_UART2_APPS_N,
  32         .D = BLSP1_UART2_APPS_D,
  33 };
  34
  35 static const struct bcr_regs sdc_regs = {
  36         .cfg_rcgr = SDCC_CFG_RCGR(1),
  37         .cmd_rcgr = SDCC_CMD_RCGR(1),
  38         .M = SDCC_M(1),
  39         .N = SDCC_N(1),
  40         .D = SDCC_D(1),
  41 };
  42
  43 static struct pll_vote_clk gpll0_vote_clk = {
  44         .status = GPLL0_STATUS,
  45         .status_bit = GPLL0_STATUS_ACTIVE,
  46         .ena_vote = APCS_GPLL_ENA_VOTE,
  47         .vote_bit = BIT(0),
  48 };
  49
  50 static const struct bcr_regs usb30_master_regs = {
  51         .cfg_rcgr = USB30_MASTER_CFG_RCGR,
  52         .cmd_rcgr = USB30_MASTER_CMD_RCGR,
  53         .M = USB30_MASTER_M,
  54         .N = USB30_MASTER_N,
  55         .D = USB30_MASTER_D,
  56 };
  57
  58 ulong msm_set_rate(struct clk *clk, ulong rate)
  59 {
  60         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  61
  62         switch (clk->id) {
  63         case GCC_BLSP1_UART2_APPS_CLK:
  64                 /* UART: 115200 */
  65                 clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
  66                                      CFG_CLK_SRC_CXO);
  67                 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
  68                 break;
  69         case GCC_BLSP1_AHB_CLK:
  70                 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
  71                 break;
  72         case GCC_SDCC1_APPS_CLK:
  73                 /* SDCC1: 200MHz */
  74                 clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
  75                                      CFG_CLK_SRC_GPLL0);
  76                 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
  77                 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
  78                 break;
  79         case GCC_SDCC1_AHB_CLK:
  80                 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
  81                 break;
  82         default:
  83                 return 0;
  84         }
  85
  86         return 0;
  87 }
  88
  89 int msm_enable(struct clk *clk)
  90 {
  91         struct msm_clk_priv *priv = dev_get_priv(clk->dev);
  92
  93         switch (clk->id) {
  94         case GCC_USB30_MASTER_CLK:
  95                 clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
  96                 clk_rcg_set_rate_mnd(priv->base, &usb30_master_regs, 4, 0, 0,
  97                                      CFG_CLK_SRC_GPLL0);
  98                 break;
  99         case GCC_SYS_NOC_USB3_CLK:
 100                 clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
 101                 break;
 102         case GCC_USB30_SLEEP_CLK:
 103                 clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
 104                 break;
 105         case GCC_USB30_MOCK_UTMI_CLK:
 106                 clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
 107                 break;
 108         case GCC_USB_HS_PHY_CFG_AHB_CLK:
 109                 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
 110                 break;
 111         case GCC_USB2A_PHY_SLEEP_CLK:
 112                 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
 113                 break;
 114         default:
 115                 return 0;
 116         }
 117
 118         return 0;
 119 }