2 * sh7372 lowlevel sleep code for "Core Standby Mode"
4 * Copyright (C) 2011 Magnus Damm
6 * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
8 * Based on mach-omap2/sleep34xx.S
10 * (C) Copyright 2007 Texas Instruments
11 * Karthik Dasu <karthik-dp@ti.com>
13 * (C) Copyright 2004 Texas Instruments, <www.ti.com>
14 * Richard Woodruff <r-woodruff2@ti.com>
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
24 * GNU General Public License for more details.
27 #include <linux/linkage.h>
28 #include <linux/init.h>
29 #include <asm/memory.h>
30 #include <asm/assembler.h>
32 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
35 .global sh7372_resume_core_standby_sysc
36 sh7372_resume_core_standby_sysc:
40 .globl sh7372_cpu_resume
44 #define SPDCR 0xe6180008
46 /* A3SM & A4S power down */
47 .global sh7372_do_idle_sysc
49 mov r8, r0 /* sleep mode passed in r0 */
52 * Clear the SCTLR.C bit to prevent further data cache
53 * allocation. Clearing SCTLR.C would make all the data accesses
54 * strongly ordered and would not hit the cache.
56 mrc p15, 0, r0, c1, c0, 0
57 bic r0, r0, #(1 << 2) @ Disable the C bit
58 mcr p15, 0, r0, c1, c0, 0
62 * Clean and invalidate data cache again.
67 /* disable L2 cache in the aux control register */
68 mrc p15, 0, r10, c1, c0, 1
70 mcr p15, 0, r10, c1, c0, 1
74 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
75 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
76 * This sequence switches back to ARM. Note that .align may insert a
77 * nop: bx pc needs to be word-aligned in order to work.
85 /* Data memory barrier and Data sync barrier */
97 .word v7_flush_dcache_all