2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/platform_data/sh_ipmmu.h>
36 #include <mach/dma-register.h>
37 #include <mach/irqs.h>
38 #include <mach/sh7372.h>
39 #include <mach/common.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh7372_io_desc[] __initdata = {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
53 .type = MT_DEVICE_NONSHARED
57 void __init sh7372_map_io(void)
59 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
63 static struct resource sh7372_pfc_resources[] = {
67 .flags = IORESOURCE_MEM,
72 .flags = IORESOURCE_MEM,
76 static struct platform_device sh7372_pfc_device = {
79 .resource = sh7372_pfc_resources,
80 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
83 void __init sh7372_pinmux_init(void)
85 platform_device_register(&sh7372_pfc_device);
89 #define SH7372_SCIF(scif_type, index, baseaddr, irq) \
90 static struct plat_sci_port scif##index##_platform_data = { \
92 .flags = UPF_BOOT_AUTOCONF, \
93 .scscr = SCSCR_RE | SCSCR_TE, \
96 static struct resource scif##index##_resources[] = { \
97 DEFINE_RES_MEM(baseaddr, 0x100), \
98 DEFINE_RES_IRQ(irq), \
101 static struct platform_device scif##index##_device = { \
104 .resource = scif##index##_resources, \
105 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 .platform_data = &scif##index##_platform_data, \
111 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
112 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
113 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
114 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
115 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
116 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
117 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
120 static struct sh_timer_config cmt2_platform_data = {
121 .channels_mask = 0x20,
124 static struct resource cmt2_resources[] = {
125 DEFINE_RES_MEM(0xe6130000, 0x50),
126 DEFINE_RES_IRQ(evt2irq(0x0b80)),
129 static struct platform_device cmt2_device = {
130 .name = "sh-cmt-32-fast",
133 .platform_data = &cmt2_platform_data,
135 .resource = cmt2_resources,
136 .num_resources = ARRAY_SIZE(cmt2_resources),
140 static struct sh_timer_config tmu0_platform_data = {
144 static struct resource tmu0_resources[] = {
145 DEFINE_RES_MEM(0xfff60000, 0x2c),
146 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
147 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
148 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
151 static struct platform_device tmu0_device = {
155 .platform_data = &tmu0_platform_data,
157 .resource = tmu0_resources,
158 .num_resources = ARRAY_SIZE(tmu0_resources),
162 static struct resource iic0_resources[] = {
166 .end = 0xFFF20425 - 1,
167 .flags = IORESOURCE_MEM,
170 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
171 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
172 .flags = IORESOURCE_IRQ,
176 static struct platform_device iic0_device = {
177 .name = "i2c-sh_mobile",
178 .id = 0, /* "i2c0" clock */
179 .num_resources = ARRAY_SIZE(iic0_resources),
180 .resource = iic0_resources,
183 static struct resource iic1_resources[] = {
187 .end = 0xE6C20425 - 1,
188 .flags = IORESOURCE_MEM,
191 .start = evt2irq(0x780), /* IIC1_ALI1 */
192 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
193 .flags = IORESOURCE_IRQ,
197 static struct platform_device iic1_device = {
198 .name = "i2c-sh_mobile",
199 .id = 1, /* "i2c1" clock */
200 .num_resources = ARRAY_SIZE(iic1_resources),
201 .resource = iic1_resources,
205 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
207 .slave_id = SHDMA_SLAVE_SCIF0_TX,
209 .chcr = CHCR_TX(XMIT_SZ_8BIT),
212 .slave_id = SHDMA_SLAVE_SCIF0_RX,
214 .chcr = CHCR_RX(XMIT_SZ_8BIT),
217 .slave_id = SHDMA_SLAVE_SCIF1_TX,
219 .chcr = CHCR_TX(XMIT_SZ_8BIT),
222 .slave_id = SHDMA_SLAVE_SCIF1_RX,
224 .chcr = CHCR_RX(XMIT_SZ_8BIT),
227 .slave_id = SHDMA_SLAVE_SCIF2_TX,
229 .chcr = CHCR_TX(XMIT_SZ_8BIT),
232 .slave_id = SHDMA_SLAVE_SCIF2_RX,
234 .chcr = CHCR_RX(XMIT_SZ_8BIT),
237 .slave_id = SHDMA_SLAVE_SCIF3_TX,
239 .chcr = CHCR_TX(XMIT_SZ_8BIT),
242 .slave_id = SHDMA_SLAVE_SCIF3_RX,
244 .chcr = CHCR_RX(XMIT_SZ_8BIT),
247 .slave_id = SHDMA_SLAVE_SCIF4_TX,
249 .chcr = CHCR_TX(XMIT_SZ_8BIT),
252 .slave_id = SHDMA_SLAVE_SCIF4_RX,
254 .chcr = CHCR_RX(XMIT_SZ_8BIT),
257 .slave_id = SHDMA_SLAVE_SCIF5_TX,
259 .chcr = CHCR_TX(XMIT_SZ_8BIT),
262 .slave_id = SHDMA_SLAVE_SCIF5_RX,
264 .chcr = CHCR_RX(XMIT_SZ_8BIT),
267 .slave_id = SHDMA_SLAVE_SCIF6_TX,
269 .chcr = CHCR_TX(XMIT_SZ_8BIT),
272 .slave_id = SHDMA_SLAVE_SCIF6_RX,
274 .chcr = CHCR_RX(XMIT_SZ_8BIT),
277 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
279 .chcr = CHCR_TX(XMIT_SZ_32BIT),
282 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
284 .chcr = CHCR_RX(XMIT_SZ_32BIT),
287 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
289 .chcr = CHCR_TX(XMIT_SZ_32BIT),
292 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
294 .chcr = CHCR_RX(XMIT_SZ_32BIT),
297 .slave_id = SHDMA_SLAVE_SDHI0_TX,
299 .chcr = CHCR_TX(XMIT_SZ_16BIT),
302 .slave_id = SHDMA_SLAVE_SDHI0_RX,
304 .chcr = CHCR_RX(XMIT_SZ_16BIT),
307 .slave_id = SHDMA_SLAVE_SDHI1_TX,
309 .chcr = CHCR_TX(XMIT_SZ_16BIT),
312 .slave_id = SHDMA_SLAVE_SDHI1_RX,
314 .chcr = CHCR_RX(XMIT_SZ_16BIT),
317 .slave_id = SHDMA_SLAVE_SDHI2_TX,
319 .chcr = CHCR_TX(XMIT_SZ_16BIT),
322 .slave_id = SHDMA_SLAVE_SDHI2_RX,
324 .chcr = CHCR_RX(XMIT_SZ_16BIT),
327 .slave_id = SHDMA_SLAVE_FSIA_TX,
329 .chcr = CHCR_TX(XMIT_SZ_32BIT),
332 .slave_id = SHDMA_SLAVE_FSIA_RX,
334 .chcr = CHCR_RX(XMIT_SZ_32BIT),
337 .slave_id = SHDMA_SLAVE_MMCIF_TX,
339 .chcr = CHCR_TX(XMIT_SZ_32BIT),
342 .slave_id = SHDMA_SLAVE_MMCIF_RX,
344 .chcr = CHCR_RX(XMIT_SZ_32BIT),
349 #define SH7372_CHCLR (0x220 - 0x20)
351 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
356 .chclr_offset = SH7372_CHCLR + 0,
361 .chclr_offset = SH7372_CHCLR + 0x10,
366 .chclr_offset = SH7372_CHCLR + 0x20,
371 .chclr_offset = SH7372_CHCLR + 0x30,
376 .chclr_offset = SH7372_CHCLR + 0x50,
381 .chclr_offset = SH7372_CHCLR + 0x60,
385 static struct sh_dmae_pdata dma_platform_data = {
386 .slave = sh7372_dmae_slaves,
387 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
388 .channel = sh7372_dmae_channels,
389 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
390 .ts_low_shift = TS_LOW_SHIFT,
391 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
392 .ts_high_shift = TS_HI_SHIFT,
393 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
394 .ts_shift = dma_ts_shift,
395 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
396 .dmaor_init = DMAOR_DME,
400 /* Resource order important! */
401 static struct resource sh7372_dmae0_resources[] = {
403 /* Channel registers and DMAOR */
406 .flags = IORESOURCE_MEM,
412 .flags = IORESOURCE_MEM,
416 .start = evt2irq(0x20c0),
417 .end = evt2irq(0x20c0),
418 .flags = IORESOURCE_IRQ,
421 /* IRQ for channels 0-5 */
422 .start = evt2irq(0x2000),
423 .end = evt2irq(0x20a0),
424 .flags = IORESOURCE_IRQ,
428 /* Resource order important! */
429 static struct resource sh7372_dmae1_resources[] = {
431 /* Channel registers and DMAOR */
434 .flags = IORESOURCE_MEM,
440 .flags = IORESOURCE_MEM,
444 .start = evt2irq(0x21c0),
445 .end = evt2irq(0x21c0),
446 .flags = IORESOURCE_IRQ,
449 /* IRQ for channels 0-5 */
450 .start = evt2irq(0x2100),
451 .end = evt2irq(0x21a0),
452 .flags = IORESOURCE_IRQ,
456 /* Resource order important! */
457 static struct resource sh7372_dmae2_resources[] = {
459 /* Channel registers and DMAOR */
462 .flags = IORESOURCE_MEM,
468 .flags = IORESOURCE_MEM,
472 .start = evt2irq(0x22c0),
473 .end = evt2irq(0x22c0),
474 .flags = IORESOURCE_IRQ,
477 /* IRQ for channels 0-5 */
478 .start = evt2irq(0x2200),
479 .end = evt2irq(0x22a0),
480 .flags = IORESOURCE_IRQ,
484 static struct platform_device dma0_device = {
485 .name = "sh-dma-engine",
487 .resource = sh7372_dmae0_resources,
488 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
490 .platform_data = &dma_platform_data,
494 static struct platform_device dma1_device = {
495 .name = "sh-dma-engine",
497 .resource = sh7372_dmae1_resources,
498 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
500 .platform_data = &dma_platform_data,
504 static struct platform_device dma2_device = {
505 .name = "sh-dma-engine",
507 .resource = sh7372_dmae2_resources,
508 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
510 .platform_data = &dma_platform_data,
517 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
526 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
528 .slave_id = SHDMA_SLAVE_USB0_TX,
529 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
531 .slave_id = SHDMA_SLAVE_USB0_RX,
532 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
536 static struct sh_dmae_pdata usb_dma0_platform_data = {
537 .slave = sh7372_usb_dmae0_slaves,
538 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
539 .channel = sh7372_usb_dmae_channels,
540 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
541 .ts_low_shift = USBTS_LOW_SHIFT,
542 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
543 .ts_high_shift = USBTS_HI_SHIFT,
544 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
545 .ts_shift = dma_usbts_shift,
546 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
547 .dmaor_init = DMAOR_DME,
549 .chcr_ie_bit = 1 << 5,
556 static struct resource sh7372_usb_dmae0_resources[] = {
558 /* Channel registers and DMAOR */
560 .end = 0xe68a0064 - 1,
561 .flags = IORESOURCE_MEM,
566 .end = 0xe68a0014 - 1,
567 .flags = IORESOURCE_MEM,
570 /* IRQ for channels */
571 .start = evt2irq(0x0a00),
572 .end = evt2irq(0x0a00),
573 .flags = IORESOURCE_IRQ,
577 static struct platform_device usb_dma0_device = {
578 .name = "sh-dma-engine",
580 .resource = sh7372_usb_dmae0_resources,
581 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
583 .platform_data = &usb_dma0_platform_data,
588 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
590 .slave_id = SHDMA_SLAVE_USB1_TX,
591 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
593 .slave_id = SHDMA_SLAVE_USB1_RX,
594 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
598 static struct sh_dmae_pdata usb_dma1_platform_data = {
599 .slave = sh7372_usb_dmae1_slaves,
600 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
601 .channel = sh7372_usb_dmae_channels,
602 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
603 .ts_low_shift = USBTS_LOW_SHIFT,
604 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
605 .ts_high_shift = USBTS_HI_SHIFT,
606 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
607 .ts_shift = dma_usbts_shift,
608 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
609 .dmaor_init = DMAOR_DME,
611 .chcr_ie_bit = 1 << 5,
618 static struct resource sh7372_usb_dmae1_resources[] = {
620 /* Channel registers and DMAOR */
622 .end = 0xe68c0064 - 1,
623 .flags = IORESOURCE_MEM,
628 .end = 0xe68c0014 - 1,
629 .flags = IORESOURCE_MEM,
632 /* IRQ for channels */
633 .start = evt2irq(0x1d00),
634 .end = evt2irq(0x1d00),
635 .flags = IORESOURCE_IRQ,
639 static struct platform_device usb_dma1_device = {
640 .name = "sh-dma-engine",
642 .resource = sh7372_usb_dmae1_resources,
643 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
645 .platform_data = &usb_dma1_platform_data,
650 static struct uio_info vpu_platform_data = {
653 .irq = intcs_evt2irq(0x980),
656 static struct resource vpu_resources[] = {
661 .flags = IORESOURCE_MEM,
665 static struct platform_device vpu_device = {
666 .name = "uio_pdrv_genirq",
669 .platform_data = &vpu_platform_data,
671 .resource = vpu_resources,
672 .num_resources = ARRAY_SIZE(vpu_resources),
676 static struct uio_info veu0_platform_data = {
679 .irq = intcs_evt2irq(0x700),
682 static struct resource veu0_resources[] = {
687 .flags = IORESOURCE_MEM,
691 static struct platform_device veu0_device = {
692 .name = "uio_pdrv_genirq",
695 .platform_data = &veu0_platform_data,
697 .resource = veu0_resources,
698 .num_resources = ARRAY_SIZE(veu0_resources),
702 static struct uio_info veu1_platform_data = {
705 .irq = intcs_evt2irq(0x720),
708 static struct resource veu1_resources[] = {
713 .flags = IORESOURCE_MEM,
717 static struct platform_device veu1_device = {
718 .name = "uio_pdrv_genirq",
721 .platform_data = &veu1_platform_data,
723 .resource = veu1_resources,
724 .num_resources = ARRAY_SIZE(veu1_resources),
728 static struct uio_info veu2_platform_data = {
731 .irq = intcs_evt2irq(0x740),
734 static struct resource veu2_resources[] = {
739 .flags = IORESOURCE_MEM,
743 static struct platform_device veu2_device = {
744 .name = "uio_pdrv_genirq",
747 .platform_data = &veu2_platform_data,
749 .resource = veu2_resources,
750 .num_resources = ARRAY_SIZE(veu2_resources),
754 static struct uio_info veu3_platform_data = {
757 .irq = intcs_evt2irq(0x760),
760 static struct resource veu3_resources[] = {
765 .flags = IORESOURCE_MEM,
769 static struct platform_device veu3_device = {
770 .name = "uio_pdrv_genirq",
773 .platform_data = &veu3_platform_data,
775 .resource = veu3_resources,
776 .num_resources = ARRAY_SIZE(veu3_resources),
780 static struct uio_info jpu_platform_data = {
783 .irq = intcs_evt2irq(0x560),
786 static struct resource jpu_resources[] = {
791 .flags = IORESOURCE_MEM,
795 static struct platform_device jpu_device = {
796 .name = "uio_pdrv_genirq",
799 .platform_data = &jpu_platform_data,
801 .resource = jpu_resources,
802 .num_resources = ARRAY_SIZE(jpu_resources),
806 static struct uio_info spu0_platform_data = {
809 .irq = evt2irq(0x1800),
812 static struct resource spu0_resources[] = {
817 .flags = IORESOURCE_MEM,
821 static struct platform_device spu0_device = {
822 .name = "uio_pdrv_genirq",
825 .platform_data = &spu0_platform_data,
827 .resource = spu0_resources,
828 .num_resources = ARRAY_SIZE(spu0_resources),
832 static struct uio_info spu1_platform_data = {
835 .irq = evt2irq(0x1820),
838 static struct resource spu1_resources[] = {
843 .flags = IORESOURCE_MEM,
847 static struct platform_device spu1_device = {
848 .name = "uio_pdrv_genirq",
851 .platform_data = &spu1_platform_data,
853 .resource = spu1_resources,
854 .num_resources = ARRAY_SIZE(spu1_resources),
857 /* IPMMUI (an IPMMU module for ICB/LMB) */
858 static struct resource ipmmu_resources[] = {
863 .flags = IORESOURCE_MEM,
867 static const char * const ipmmu_dev_names[] = {
868 "sh_mobile_lcdc_fb.0",
869 "sh_mobile_lcdc_fb.1",
879 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
880 .dev_names = ipmmu_dev_names,
881 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
884 static struct platform_device ipmmu_device = {
888 .platform_data = &ipmmu_platform_data,
890 .resource = ipmmu_resources,
891 .num_resources = ARRAY_SIZE(ipmmu_resources),
894 static struct platform_device *sh7372_early_devices[] __initdata = {
907 static struct platform_device *sh7372_late_devices[] __initdata = {
925 void __init sh7372_add_standard_devices(void)
927 struct pm_domain_device domain_devices[] = {
928 { "A3RV", &vpu_device, },
929 { "A4MP", &spu0_device, },
930 { "A4MP", &spu1_device, },
931 { "A3SP", &scif0_device, },
932 { "A3SP", &scif1_device, },
933 { "A3SP", &scif2_device, },
934 { "A3SP", &scif3_device, },
935 { "A3SP", &scif4_device, },
936 { "A3SP", &scif5_device, },
937 { "A3SP", &scif6_device, },
938 { "A3SP", &iic1_device, },
939 { "A3SP", &dma0_device, },
940 { "A3SP", &dma1_device, },
941 { "A3SP", &dma2_device, },
942 { "A3SP", &usb_dma0_device, },
943 { "A3SP", &usb_dma1_device, },
944 { "A4R", &iic0_device, },
945 { "A4R", &veu0_device, },
946 { "A4R", &veu1_device, },
947 { "A4R", &veu2_device, },
948 { "A4R", &veu3_device, },
949 { "A4R", &jpu_device, },
950 { "A4R", &tmu0_device, },
953 sh7372_init_pm_domains();
955 platform_add_devices(sh7372_early_devices,
956 ARRAY_SIZE(sh7372_early_devices));
958 platform_add_devices(sh7372_late_devices,
959 ARRAY_SIZE(sh7372_late_devices));
961 rmobile_add_devices_to_domains(domain_devices,
962 ARRAY_SIZE(domain_devices));
965 void __init sh7372_earlytimer_init(void)
968 shmobile_earlytimer_init();
971 void __init sh7372_add_early_devices(void)
973 early_platform_add_devices(sh7372_early_devices,
974 ARRAY_SIZE(sh7372_early_devices));
976 /* setup early console here as well */
977 shmobile_setup_console();
982 void __init sh7372_add_early_devices_dt(void)
984 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
986 sh7372_add_early_devices();
989 void __init sh7372_add_standard_devices_dt(void)
991 /* clocks are setup late during boot in the case of DT */
994 platform_add_devices(sh7372_early_devices,
995 ARRAY_SIZE(sh7372_early_devices));
997 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1000 static const char *sh7372_boards_compat_dt[] __initdata = {
1005 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1006 .map_io = sh7372_map_io,
1007 .init_early = sh7372_add_early_devices_dt,
1008 .nr_irqs = NR_IRQS_LEGACY,
1009 .init_irq = sh7372_init_irq,
1010 .handle_irq = shmobile_handle_irq_intc,
1011 .init_machine = sh7372_add_standard_devices_dt,
1012 .dt_compat = sh7372_boards_compat_dt,
1015 #endif /* CONFIG_USE_OF */