2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/delay.h>
26 #include <linux/input.h>
28 #include <linux/serial_sci.h>
29 #include <linux/sh_dma.h>
30 #include <linux/sh_intc.h>
31 #include <linux/sh_timer.h>
32 #include <mach/hardware.h>
33 #include <mach/sh7372.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
38 static struct plat_sci_port scif0_platform_data = {
39 .mapbase = 0xe6c40000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
43 evt2irq(0x0c00), evt2irq(0x0c00) },
46 static struct platform_device scif0_device = {
50 .platform_data = &scif0_platform_data,
55 static struct plat_sci_port scif1_platform_data = {
56 .mapbase = 0xe6c50000,
57 .flags = UPF_BOOT_AUTOCONF,
59 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
60 evt2irq(0x0c20), evt2irq(0x0c20) },
63 static struct platform_device scif1_device = {
67 .platform_data = &scif1_platform_data,
72 static struct plat_sci_port scif2_platform_data = {
73 .mapbase = 0xe6c60000,
74 .flags = UPF_BOOT_AUTOCONF,
76 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
77 evt2irq(0x0c40), evt2irq(0x0c40) },
80 static struct platform_device scif2_device = {
84 .platform_data = &scif2_platform_data,
89 static struct plat_sci_port scif3_platform_data = {
90 .mapbase = 0xe6c70000,
91 .flags = UPF_BOOT_AUTOCONF,
93 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
94 evt2irq(0x0c60), evt2irq(0x0c60) },
97 static struct platform_device scif3_device = {
101 .platform_data = &scif3_platform_data,
106 static struct plat_sci_port scif4_platform_data = {
107 .mapbase = 0xe6c80000,
108 .flags = UPF_BOOT_AUTOCONF,
110 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
111 evt2irq(0x0d20), evt2irq(0x0d20) },
114 static struct platform_device scif4_device = {
118 .platform_data = &scif4_platform_data,
123 static struct plat_sci_port scif5_platform_data = {
124 .mapbase = 0xe6cb0000,
125 .flags = UPF_BOOT_AUTOCONF,
127 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
128 evt2irq(0x0d40), evt2irq(0x0d40) },
131 static struct platform_device scif5_device = {
135 .platform_data = &scif5_platform_data,
140 static struct plat_sci_port scif6_platform_data = {
141 .mapbase = 0xe6c30000,
142 .flags = UPF_BOOT_AUTOCONF,
144 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
145 evt2irq(0x0d60), evt2irq(0x0d60) },
148 static struct platform_device scif6_device = {
152 .platform_data = &scif6_platform_data,
157 static struct sh_timer_config cmt10_platform_data = {
159 .channel_offset = 0x10,
161 .clockevent_rating = 125,
162 .clocksource_rating = 125,
165 static struct resource cmt10_resources[] = {
170 .flags = IORESOURCE_MEM,
173 .start = evt2irq(0x0b00), /* CMT1_CMT10 */
174 .flags = IORESOURCE_IRQ,
178 static struct platform_device cmt10_device = {
182 .platform_data = &cmt10_platform_data,
184 .resource = cmt10_resources,
185 .num_resources = ARRAY_SIZE(cmt10_resources),
189 static struct sh_timer_config tmu00_platform_data = {
191 .channel_offset = 0x4,
193 .clockevent_rating = 200,
196 static struct resource tmu00_resources[] = {
201 .flags = IORESOURCE_MEM,
204 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device tmu00_device = {
213 .platform_data = &tmu00_platform_data,
215 .resource = tmu00_resources,
216 .num_resources = ARRAY_SIZE(tmu00_resources),
219 static struct sh_timer_config tmu01_platform_data = {
221 .channel_offset = 0x10,
223 .clocksource_rating = 200,
226 static struct resource tmu01_resources[] = {
231 .flags = IORESOURCE_MEM,
234 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
235 .flags = IORESOURCE_IRQ,
239 static struct platform_device tmu01_device = {
243 .platform_data = &tmu01_platform_data,
245 .resource = tmu01_resources,
246 .num_resources = ARRAY_SIZE(tmu01_resources),
250 static struct resource iic0_resources[] = {
254 .end = 0xFFF20425 - 1,
255 .flags = IORESOURCE_MEM,
258 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
259 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
260 .flags = IORESOURCE_IRQ,
264 static struct platform_device iic0_device = {
265 .name = "i2c-sh_mobile",
266 .id = 0, /* "i2c0" clock */
267 .num_resources = ARRAY_SIZE(iic0_resources),
268 .resource = iic0_resources,
271 static struct resource iic1_resources[] = {
275 .end = 0xE6C20425 - 1,
276 .flags = IORESOURCE_MEM,
279 .start = evt2irq(0x780), /* IIC1_ALI1 */
280 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
281 .flags = IORESOURCE_IRQ,
285 static struct platform_device iic1_device = {
286 .name = "i2c-sh_mobile",
287 .id = 1, /* "i2c1" clock */
288 .num_resources = ARRAY_SIZE(iic1_resources),
289 .resource = iic1_resources,
293 /* Transmit sizes and respective CHCR register values */
304 /* log2(size / 8) - used to calculate number of transfers */
306 [XMIT_SZ_8BIT] = 0, \
307 [XMIT_SZ_16BIT] = 1, \
308 [XMIT_SZ_32BIT] = 2, \
309 [XMIT_SZ_64BIT] = 3, \
310 [XMIT_SZ_128BIT] = 4, \
311 [XMIT_SZ_256BIT] = 5, \
312 [XMIT_SZ_512BIT] = 6, \
315 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
316 (((i) & 0xc) << (20 - 2)))
318 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
320 .slave_id = SHDMA_SLAVE_SCIF0_TX,
322 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
325 .slave_id = SHDMA_SLAVE_SCIF0_RX,
327 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
330 .slave_id = SHDMA_SLAVE_SCIF1_TX,
332 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
335 .slave_id = SHDMA_SLAVE_SCIF1_RX,
337 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_SCIF2_TX,
342 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
345 .slave_id = SHDMA_SLAVE_SCIF2_RX,
347 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
350 .slave_id = SHDMA_SLAVE_SCIF3_TX,
352 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
355 .slave_id = SHDMA_SLAVE_SCIF3_RX,
357 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
360 .slave_id = SHDMA_SLAVE_SCIF4_TX,
362 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
365 .slave_id = SHDMA_SLAVE_SCIF4_RX,
367 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
370 .slave_id = SHDMA_SLAVE_SCIF5_TX,
372 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
375 .slave_id = SHDMA_SLAVE_SCIF5_RX,
377 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
380 .slave_id = SHDMA_SLAVE_SCIF6_TX,
382 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
385 .slave_id = SHDMA_SLAVE_SCIF6_RX,
387 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
390 .slave_id = SHDMA_SLAVE_SDHI0_TX,
392 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
395 .slave_id = SHDMA_SLAVE_SDHI0_RX,
397 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
400 .slave_id = SHDMA_SLAVE_SDHI1_TX,
402 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
405 .slave_id = SHDMA_SLAVE_SDHI1_RX,
407 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
410 .slave_id = SHDMA_SLAVE_SDHI2_TX,
412 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
415 .slave_id = SHDMA_SLAVE_SDHI2_RX,
417 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
420 .slave_id = SHDMA_SLAVE_MMCIF_TX,
422 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
425 .slave_id = SHDMA_SLAVE_MMCIF_RX,
427 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
432 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
460 static const unsigned int ts_shift[] = TS_SHIFT;
462 static struct sh_dmae_pdata dma_platform_data = {
463 .slave = sh7372_dmae_slaves,
464 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
465 .channel = sh7372_dmae_channels,
466 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
469 .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
470 .ts_high_mask = 0x00300000,
471 .ts_shift = ts_shift,
472 .ts_shift_num = ARRAY_SIZE(ts_shift),
473 .dmaor_init = DMAOR_DME,
476 /* Resource order important! */
477 static struct resource sh7372_dmae0_resources[] = {
479 /* Channel registers and DMAOR */
482 .flags = IORESOURCE_MEM,
488 .flags = IORESOURCE_MEM,
492 .start = evt2irq(0x20c0),
493 .end = evt2irq(0x20c0),
494 .flags = IORESOURCE_IRQ,
497 /* IRQ for channels 0-5 */
498 .start = evt2irq(0x2000),
499 .end = evt2irq(0x20a0),
500 .flags = IORESOURCE_IRQ,
504 /* Resource order important! */
505 static struct resource sh7372_dmae1_resources[] = {
507 /* Channel registers and DMAOR */
510 .flags = IORESOURCE_MEM,
516 .flags = IORESOURCE_MEM,
520 .start = evt2irq(0x21c0),
521 .end = evt2irq(0x21c0),
522 .flags = IORESOURCE_IRQ,
525 /* IRQ for channels 0-5 */
526 .start = evt2irq(0x2100),
527 .end = evt2irq(0x21a0),
528 .flags = IORESOURCE_IRQ,
532 /* Resource order important! */
533 static struct resource sh7372_dmae2_resources[] = {
535 /* Channel registers and DMAOR */
538 .flags = IORESOURCE_MEM,
544 .flags = IORESOURCE_MEM,
548 .start = evt2irq(0x22c0),
549 .end = evt2irq(0x22c0),
550 .flags = IORESOURCE_IRQ,
553 /* IRQ for channels 0-5 */
554 .start = evt2irq(0x2200),
555 .end = evt2irq(0x22a0),
556 .flags = IORESOURCE_IRQ,
560 static struct platform_device dma0_device = {
561 .name = "sh-dma-engine",
563 .resource = sh7372_dmae0_resources,
564 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
566 .platform_data = &dma_platform_data,
570 static struct platform_device dma1_device = {
571 .name = "sh-dma-engine",
573 .resource = sh7372_dmae1_resources,
574 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
576 .platform_data = &dma_platform_data,
580 static struct platform_device dma2_device = {
581 .name = "sh-dma-engine",
583 .resource = sh7372_dmae2_resources,
584 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
586 .platform_data = &dma_platform_data,
590 static struct platform_device *sh7372_early_devices[] __initdata = {
603 static struct platform_device *sh7372_late_devices[] __initdata = {
611 void __init sh7372_add_standard_devices(void)
613 platform_add_devices(sh7372_early_devices,
614 ARRAY_SIZE(sh7372_early_devices));
616 platform_add_devices(sh7372_late_devices,
617 ARRAY_SIZE(sh7372_late_devices));
620 void __init sh7372_add_early_devices(void)
622 early_platform_add_devices(sh7372_early_devices,
623 ARRAY_SIZE(sh7372_early_devices));