arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_intc.h>
  33 #include <linux/sh_timer.h>
  34 #include <linux/pm_domain.h>
  35 #include <linux/dma-mapping.h>
  36 #include <mach/dma-register.h>
  37 #include <mach/hardware.h>
  38 #include <mach/irqs.h>
  39 #include <mach/sh7372.h>
  40 #include <mach/common.h>
  41 #include <asm/mach/map.h>
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/time.h>
  45
  46 static struct map_desc sh7372_io_desc[] __initdata = {
  47         /* create a 1:1 entity map for 0xe6xxxxxx
  48          * used by CPGA, INTC and PFC.
  49          */
  50         {
  51                 .virtual        = 0xe6000000,
  52                 .pfn            = __phys_to_pfn(0xe6000000),
  53                 .length         = 256 << 20,
  54                 .type           = MT_DEVICE_NONSHARED
  55         },
  56 };
  57
  58 void __init sh7372_map_io(void)
  59 {
  60         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  61 }
  62
  63 /* SCIFA0 */
  64 static struct plat_sci_port scif0_platform_data = {
  65         .mapbase        = 0xe6c40000,
  66         .flags          = UPF_BOOT_AUTOCONF,
  67         .scscr          = SCSCR_RE | SCSCR_TE,
  68         .scbrr_algo_id  = SCBRR_ALGO_4,
  69         .type           = PORT_SCIFA,
  70         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  71                             evt2irq(0x0c00), evt2irq(0x0c00) },
  72 };
  73
  74 static struct platform_device scif0_device = {
  75         .name           = "sh-sci",
  76         .id             = 0,
  77         .dev            = {
  78                 .platform_data  = &scif0_platform_data,
  79         },
  80 };
  81
  82 /* SCIFA1 */
  83 static struct plat_sci_port scif1_platform_data = {
  84         .mapbase        = 0xe6c50000,
  85         .flags          = UPF_BOOT_AUTOCONF,
  86         .scscr          = SCSCR_RE | SCSCR_TE,
  87         .scbrr_algo_id  = SCBRR_ALGO_4,
  88         .type           = PORT_SCIFA,
  89         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  90                             evt2irq(0x0c20), evt2irq(0x0c20) },
  91 };
  92
  93 static struct platform_device scif1_device = {
  94         .name           = "sh-sci",
  95         .id             = 1,
  96         .dev            = {
  97                 .platform_data  = &scif1_platform_data,
  98         },
  99 };
 100
 101 /* SCIFA2 */
 102 static struct plat_sci_port scif2_platform_data = {
 103         .mapbase        = 0xe6c60000,
 104         .flags          = UPF_BOOT_AUTOCONF,
 105         .scscr          = SCSCR_RE | SCSCR_TE,
 106         .scbrr_algo_id  = SCBRR_ALGO_4,
 107         .type           = PORT_SCIFA,
 108         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
 109                             evt2irq(0x0c40), evt2irq(0x0c40) },
 110 };
 111
 112 static struct platform_device scif2_device = {
 113         .name           = "sh-sci",
 114         .id             = 2,
 115         .dev            = {
 116                 .platform_data  = &scif2_platform_data,
 117         },
 118 };
 119
 120 /* SCIFA3 */
 121 static struct plat_sci_port scif3_platform_data = {
 122         .mapbase        = 0xe6c70000,
 123         .flags          = UPF_BOOT_AUTOCONF,
 124         .scscr          = SCSCR_RE | SCSCR_TE,
 125         .scbrr_algo_id  = SCBRR_ALGO_4,
 126         .type           = PORT_SCIFA,
 127         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
 128                             evt2irq(0x0c60), evt2irq(0x0c60) },
 129 };
 130
 131 static struct platform_device scif3_device = {
 132         .name           = "sh-sci",
 133         .id             = 3,
 134         .dev            = {
 135                 .platform_data  = &scif3_platform_data,
 136         },
 137 };
 138
 139 /* SCIFA4 */
 140 static struct plat_sci_port scif4_platform_data = {
 141         .mapbase        = 0xe6c80000,
 142         .flags          = UPF_BOOT_AUTOCONF,
 143         .scscr          = SCSCR_RE | SCSCR_TE,
 144         .scbrr_algo_id  = SCBRR_ALGO_4,
 145         .type           = PORT_SCIFA,
 146         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 147                             evt2irq(0x0d20), evt2irq(0x0d20) },
 148 };
 149
 150 static struct platform_device scif4_device = {
 151         .name           = "sh-sci",
 152         .id             = 4,
 153         .dev            = {
 154                 .platform_data  = &scif4_platform_data,
 155         },
 156 };
 157
 158 /* SCIFA5 */
 159 static struct plat_sci_port scif5_platform_data = {
 160         .mapbase        = 0xe6cb0000,
 161         .flags          = UPF_BOOT_AUTOCONF,
 162         .scscr          = SCSCR_RE | SCSCR_TE,
 163         .scbrr_algo_id  = SCBRR_ALGO_4,
 164         .type           = PORT_SCIFA,
 165         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 166                             evt2irq(0x0d40), evt2irq(0x0d40) },
 167 };
 168
 169 static struct platform_device scif5_device = {
 170         .name           = "sh-sci",
 171         .id             = 5,
 172         .dev            = {
 173                 .platform_data  = &scif5_platform_data,
 174         },
 175 };
 176
 177 /* SCIFB */
 178 static struct plat_sci_port scif6_platform_data = {
 179         .mapbase        = 0xe6c30000,
 180         .flags          = UPF_BOOT_AUTOCONF,
 181         .scscr          = SCSCR_RE | SCSCR_TE,
 182         .scbrr_algo_id  = SCBRR_ALGO_4,
 183         .type           = PORT_SCIFB,
 184         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 185                             evt2irq(0x0d60), evt2irq(0x0d60) },
 186 };
 187
 188 static struct platform_device scif6_device = {
 189         .name           = "sh-sci",
 190         .id             = 6,
 191         .dev            = {
 192                 .platform_data  = &scif6_platform_data,
 193         },
 194 };
 195
 196 /* CMT */
 197 static struct sh_timer_config cmt2_platform_data = {
 198         .name = "CMT2",
 199         .channel_offset = 0x40,
 200         .timer_bit = 5,
 201         .clockevent_rating = 125,
 202         .clocksource_rating = 125,
 203 };
 204
 205 static struct resource cmt2_resources[] = {
 206         [0] = {
 207                 .name   = "CMT2",
 208                 .start  = 0xe6130040,
 209                 .end    = 0xe613004b,
 210                 .flags  = IORESOURCE_MEM,
 211         },
 212         [1] = {
 213                 .start  = evt2irq(0x0b80), /* CMT2 */
 214                 .flags  = IORESOURCE_IRQ,
 215         },
 216 };
 217
 218 static struct platform_device cmt2_device = {
 219         .name           = "sh_cmt",
 220         .id             = 2,
 221         .dev = {
 222                 .platform_data  = &cmt2_platform_data,
 223         },
 224         .resource       = cmt2_resources,
 225         .num_resources  = ARRAY_SIZE(cmt2_resources),
 226 };
 227
 228 /* TMU */
 229 static struct sh_timer_config tmu00_platform_data = {
 230         .name = "TMU00",
 231         .channel_offset = 0x4,
 232         .timer_bit = 0,
 233         .clockevent_rating = 200,
 234 };
 235
 236 static struct resource tmu00_resources[] = {
 237         [0] = {
 238                 .name   = "TMU00",
 239                 .start  = 0xfff60008,
 240                 .end    = 0xfff60013,
 241                 .flags  = IORESOURCE_MEM,
 242         },
 243         [1] = {
 244                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
 245                 .flags  = IORESOURCE_IRQ,
 246         },
 247 };
 248
 249 static struct platform_device tmu00_device = {
 250         .name           = "sh_tmu",
 251         .id             = 0,
 252         .dev = {
 253                 .platform_data  = &tmu00_platform_data,
 254         },
 255         .resource       = tmu00_resources,
 256         .num_resources  = ARRAY_SIZE(tmu00_resources),
 257 };
 258
 259 static struct sh_timer_config tmu01_platform_data = {
 260         .name = "TMU01",
 261         .channel_offset = 0x10,
 262         .timer_bit = 1,
 263         .clocksource_rating = 200,
 264 };
 265
 266 static struct resource tmu01_resources[] = {
 267         [0] = {
 268                 .name   = "TMU01",
 269                 .start  = 0xfff60014,
 270                 .end    = 0xfff6001f,
 271                 .flags  = IORESOURCE_MEM,
 272         },
 273         [1] = {
 274                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
 275                 .flags  = IORESOURCE_IRQ,
 276         },
 277 };
 278
 279 static struct platform_device tmu01_device = {
 280         .name           = "sh_tmu",
 281         .id             = 1,
 282         .dev = {
 283                 .platform_data  = &tmu01_platform_data,
 284         },
 285         .resource       = tmu01_resources,
 286         .num_resources  = ARRAY_SIZE(tmu01_resources),
 287 };
 288
 289 /* I2C */
 290 static struct resource iic0_resources[] = {
 291         [0] = {
 292                 .name   = "IIC0",
 293                 .start  = 0xFFF20000,
 294                 .end    = 0xFFF20425 - 1,
 295                 .flags  = IORESOURCE_MEM,
 296         },
 297         [1] = {
 298                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 299                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 300                 .flags  = IORESOURCE_IRQ,
 301         },
 302 };
 303
 304 static struct platform_device iic0_device = {
 305         .name           = "i2c-sh_mobile",
 306         .id             = 0, /* "i2c0" clock */
 307         .num_resources  = ARRAY_SIZE(iic0_resources),
 308         .resource       = iic0_resources,
 309 };
 310
 311 static struct resource iic1_resources[] = {
 312         [0] = {
 313                 .name   = "IIC1",
 314                 .start  = 0xE6C20000,
 315                 .end    = 0xE6C20425 - 1,
 316                 .flags  = IORESOURCE_MEM,
 317         },
 318         [1] = {
 319                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 320                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 321                 .flags  = IORESOURCE_IRQ,
 322         },
 323 };
 324
 325 static struct platform_device iic1_device = {
 326         .name           = "i2c-sh_mobile",
 327         .id             = 1, /* "i2c1" clock */
 328         .num_resources  = ARRAY_SIZE(iic1_resources),
 329         .resource       = iic1_resources,
 330 };
 331
 332 /* DMA */
 333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 334         {
 335                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 336                 .addr           = 0xe6c40020,
 337                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 338                 .mid_rid        = 0x21,
 339         }, {
 340                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 341                 .addr           = 0xe6c40024,
 342                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 343                 .mid_rid        = 0x22,
 344         }, {
 345                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 346                 .addr           = 0xe6c50020,
 347                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 348                 .mid_rid        = 0x25,
 349         }, {
 350                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 351                 .addr           = 0xe6c50024,
 352                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 353                 .mid_rid        = 0x26,
 354         }, {
 355                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 356                 .addr           = 0xe6c60020,
 357                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 358                 .mid_rid        = 0x29,
 359         }, {
 360                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 361                 .addr           = 0xe6c60024,
 362                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 363                 .mid_rid        = 0x2a,
 364         }, {
 365                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 366                 .addr           = 0xe6c70020,
 367                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 368                 .mid_rid        = 0x2d,
 369         }, {
 370                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 371                 .addr           = 0xe6c70024,
 372                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 373                 .mid_rid        = 0x2e,
 374         }, {
 375                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 376                 .addr           = 0xe6c80020,
 377                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 378                 .mid_rid        = 0x39,
 379         }, {
 380                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 381                 .addr           = 0xe6c80024,
 382                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 383                 .mid_rid        = 0x3a,
 384         }, {
 385                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 386                 .addr           = 0xe6cb0020,
 387                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 388                 .mid_rid        = 0x35,
 389         }, {
 390                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 391                 .addr           = 0xe6cb0024,
 392                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 393                 .mid_rid        = 0x36,
 394         }, {
 395                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 396                 .addr           = 0xe6c30040,
 397                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 398                 .mid_rid        = 0x3d,
 399         }, {
 400                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 401                 .addr           = 0xe6c30060,
 402                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 403                 .mid_rid        = 0x3e,
 404         }, {
 405                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 406                 .addr           = 0xe6850030,
 407                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 408                 .mid_rid        = 0xc1,
 409         }, {
 410                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 411                 .addr           = 0xe6850030,
 412                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 413                 .mid_rid        = 0xc2,
 414         }, {
 415                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 416                 .addr           = 0xe6860030,
 417                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 418                 .mid_rid        = 0xc9,
 419         }, {
 420                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 421                 .addr           = 0xe6860030,
 422                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 423                 .mid_rid        = 0xca,
 424         }, {
 425                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 426                 .addr           = 0xe6870030,
 427                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 428                 .mid_rid        = 0xcd,
 429         }, {
 430                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 431                 .addr           = 0xe6870030,
 432                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 433                 .mid_rid        = 0xce,
 434         }, {
 435                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 436                 .addr           = 0xfe1f0024,
 437                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 438                 .mid_rid        = 0xb1,
 439         }, {
 440                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 441                 .addr           = 0xfe1f0020,
 442                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 443                 .mid_rid        = 0xb2,
 444         }, {
 445                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 446                 .addr           = 0xe6bd0034,
 447                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 448                 .mid_rid        = 0xd1,
 449         }, {
 450                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 451                 .addr           = 0xe6bd0034,
 452                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 453                 .mid_rid        = 0xd2,
 454         },
 455 };
 456
 457 #define SH7372_CHCLR (0x220 - 0x20)
 458
 459 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 460         {
 461                 .offset = 0,
 462                 .dmars = 0,
 463                 .dmars_bit = 0,
 464                 .chclr_offset = SH7372_CHCLR + 0,
 465         }, {
 466                 .offset = 0x10,
 467                 .dmars = 0,
 468                 .dmars_bit = 8,
 469                 .chclr_offset = SH7372_CHCLR + 0x10,
 470         }, {
 471                 .offset = 0x20,
 472                 .dmars = 4,
 473                 .dmars_bit = 0,
 474                 .chclr_offset = SH7372_CHCLR + 0x20,
 475         }, {
 476                 .offset = 0x30,
 477                 .dmars = 4,
 478                 .dmars_bit = 8,
 479                 .chclr_offset = SH7372_CHCLR + 0x30,
 480         }, {
 481                 .offset = 0x50,
 482                 .dmars = 8,
 483                 .dmars_bit = 0,
 484                 .chclr_offset = SH7372_CHCLR + 0x50,
 485         }, {
 486                 .offset = 0x60,
 487                 .dmars = 8,
 488                 .dmars_bit = 8,
 489                 .chclr_offset = SH7372_CHCLR + 0x60,
 490         }
 491 };
 492
 493 static struct sh_dmae_pdata dma_platform_data = {
 494         .slave          = sh7372_dmae_slaves,
 495         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 496         .channel        = sh7372_dmae_channels,
 497         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 498         .ts_low_shift   = TS_LOW_SHIFT,
 499         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 500         .ts_high_shift  = TS_HI_SHIFT,
 501         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 502         .ts_shift       = dma_ts_shift,
 503         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 504         .dmaor_init     = DMAOR_DME,
 505         .chclr_present  = 1,
 506 };
 507
 508 /* Resource order important! */
 509 static struct resource sh7372_dmae0_resources[] = {
 510         {
 511                 /* Channel registers and DMAOR */
 512                 .start  = 0xfe008020,
 513                 .end    = 0xfe00828f,
 514                 .flags  = IORESOURCE_MEM,
 515         },
 516         {
 517                 /* DMARSx */
 518                 .start  = 0xfe009000,
 519                 .end    = 0xfe00900b,
 520                 .flags  = IORESOURCE_MEM,
 521         },
 522         {
 523                 .name   = "error_irq",
 524                 .start  = evt2irq(0x20c0),
 525                 .end    = evt2irq(0x20c0),
 526                 .flags  = IORESOURCE_IRQ,
 527         },
 528         {
 529                 /* IRQ for channels 0-5 */
 530                 .start  = evt2irq(0x2000),
 531                 .end    = evt2irq(0x20a0),
 532                 .flags  = IORESOURCE_IRQ,
 533         },
 534 };
 535
 536 /* Resource order important! */
 537 static struct resource sh7372_dmae1_resources[] = {
 538         {
 539                 /* Channel registers and DMAOR */
 540                 .start  = 0xfe018020,
 541                 .end    = 0xfe01828f,
 542                 .flags  = IORESOURCE_MEM,
 543         },
 544         {
 545                 /* DMARSx */
 546                 .start  = 0xfe019000,
 547                 .end    = 0xfe01900b,
 548                 .flags  = IORESOURCE_MEM,
 549         },
 550         {
 551                 .name   = "error_irq",
 552                 .start  = evt2irq(0x21c0),
 553                 .end    = evt2irq(0x21c0),
 554                 .flags  = IORESOURCE_IRQ,
 555         },
 556         {
 557                 /* IRQ for channels 0-5 */
 558                 .start  = evt2irq(0x2100),
 559                 .end    = evt2irq(0x21a0),
 560                 .flags  = IORESOURCE_IRQ,
 561         },
 562 };
 563
 564 /* Resource order important! */
 565 static struct resource sh7372_dmae2_resources[] = {
 566         {
 567                 /* Channel registers and DMAOR */
 568                 .start  = 0xfe028020,
 569                 .end    = 0xfe02828f,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         {
 573                 /* DMARSx */
 574                 .start  = 0xfe029000,
 575                 .end    = 0xfe02900b,
 576                 .flags  = IORESOURCE_MEM,
 577         },
 578         {
 579                 .name   = "error_irq",
 580                 .start  = evt2irq(0x22c0),
 581                 .end    = evt2irq(0x22c0),
 582                 .flags  = IORESOURCE_IRQ,
 583         },
 584         {
 585                 /* IRQ for channels 0-5 */
 586                 .start  = evt2irq(0x2200),
 587                 .end    = evt2irq(0x22a0),
 588                 .flags  = IORESOURCE_IRQ,
 589         },
 590 };
 591
 592 static struct platform_device dma0_device = {
 593         .name           = "sh-dma-engine",
 594         .id             = 0,
 595         .resource       = sh7372_dmae0_resources,
 596         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 597         .dev            = {
 598                 .platform_data  = &dma_platform_data,
 599         },
 600 };
 601
 602 static struct platform_device dma1_device = {
 603         .name           = "sh-dma-engine",
 604         .id             = 1,
 605         .resource       = sh7372_dmae1_resources,
 606         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 607         .dev            = {
 608                 .platform_data  = &dma_platform_data,
 609         },
 610 };
 611
 612 static struct platform_device dma2_device = {
 613         .name           = "sh-dma-engine",
 614         .id             = 2,
 615         .resource       = sh7372_dmae2_resources,
 616         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 617         .dev            = {
 618                 .platform_data  = &dma_platform_data,
 619         },
 620 };
 621
 622 /*
 623  * USB-DMAC
 624  */
 625 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 626         {
 627                 .offset = 0,
 628         }, {
 629                 .offset = 0x20,
 630         },
 631 };
 632
 633 /* USB DMAC0 */
 634 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 635         {
 636                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 637                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 638         }, {
 639                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 640                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 641         },
 642 };
 643
 644 static struct sh_dmae_pdata usb_dma0_platform_data = {
 645         .slave          = sh7372_usb_dmae0_slaves,
 646         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 647         .channel        = sh7372_usb_dmae_channels,
 648         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 649         .ts_low_shift   = USBTS_LOW_SHIFT,
 650         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 651         .ts_high_shift  = USBTS_HI_SHIFT,
 652         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 653         .ts_shift       = dma_usbts_shift,
 654         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 655         .dmaor_init     = DMAOR_DME,
 656         .chcr_offset    = 0x14,
 657         .chcr_ie_bit    = 1 << 5,
 658         .dmaor_is_32bit = 1,
 659         .needs_tend_set = 1,
 660         .no_dmars       = 1,
 661         .slave_only     = 1,
 662 };
 663
 664 static struct resource sh7372_usb_dmae0_resources[] = {
 665         {
 666                 /* Channel registers and DMAOR */
 667                 .start  = 0xe68a0020,
 668                 .end    = 0xe68a0064 - 1,
 669                 .flags  = IORESOURCE_MEM,
 670         },
 671         {
 672                 /* VCR/SWR/DMICR */
 673                 .start  = 0xe68a0000,
 674                 .end    = 0xe68a0014 - 1,
 675                 .flags  = IORESOURCE_MEM,
 676         },
 677         {
 678                 /* IRQ for channels */
 679                 .start  = evt2irq(0x0a00),
 680                 .end    = evt2irq(0x0a00),
 681                 .flags  = IORESOURCE_IRQ,
 682         },
 683 };
 684
 685 static struct platform_device usb_dma0_device = {
 686         .name           = "sh-dma-engine",
 687         .id             = 3,
 688         .resource       = sh7372_usb_dmae0_resources,
 689         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 690         .dev            = {
 691                 .platform_data  = &usb_dma0_platform_data,
 692         },
 693 };
 694
 695 /* USB DMAC1 */
 696 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 697         {
 698                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 699                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 700         }, {
 701                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 702                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 703         },
 704 };
 705
 706 static struct sh_dmae_pdata usb_dma1_platform_data = {
 707         .slave          = sh7372_usb_dmae1_slaves,
 708         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 709         .channel        = sh7372_usb_dmae_channels,
 710         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 711         .ts_low_shift   = USBTS_LOW_SHIFT,
 712         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 713         .ts_high_shift  = USBTS_HI_SHIFT,
 714         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 715         .ts_shift       = dma_usbts_shift,
 716         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 717         .dmaor_init     = DMAOR_DME,
 718         .chcr_offset    = 0x14,
 719         .chcr_ie_bit    = 1 << 5,
 720         .dmaor_is_32bit = 1,
 721         .needs_tend_set = 1,
 722         .no_dmars       = 1,
 723         .slave_only     = 1,
 724 };
 725
 726 static struct resource sh7372_usb_dmae1_resources[] = {
 727         {
 728                 /* Channel registers and DMAOR */
 729                 .start  = 0xe68c0020,
 730                 .end    = 0xe68c0064 - 1,
 731                 .flags  = IORESOURCE_MEM,
 732         },
 733         {
 734                 /* VCR/SWR/DMICR */
 735                 .start  = 0xe68c0000,
 736                 .end    = 0xe68c0014 - 1,
 737                 .flags  = IORESOURCE_MEM,
 738         },
 739         {
 740                 /* IRQ for channels */
 741                 .start  = evt2irq(0x1d00),
 742                 .end    = evt2irq(0x1d00),
 743                 .flags  = IORESOURCE_IRQ,
 744         },
 745 };
 746
 747 static struct platform_device usb_dma1_device = {
 748         .name           = "sh-dma-engine",
 749         .id             = 4,
 750         .resource       = sh7372_usb_dmae1_resources,
 751         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 752         .dev            = {
 753                 .platform_data  = &usb_dma1_platform_data,
 754         },
 755 };
 756
 757 /* VPU */
 758 static struct uio_info vpu_platform_data = {
 759         .name = "VPU5HG",
 760         .version = "0",
 761         .irq = intcs_evt2irq(0x980),
 762 };
 763
 764 static struct resource vpu_resources[] = {
 765         [0] = {
 766                 .name   = "VPU",
 767                 .start  = 0xfe900000,
 768                 .end    = 0xfe900157,
 769                 .flags  = IORESOURCE_MEM,
 770         },
 771 };
 772
 773 static struct platform_device vpu_device = {
 774         .name           = "uio_pdrv_genirq",
 775         .id             = 0,
 776         .dev = {
 777                 .platform_data  = &vpu_platform_data,
 778         },
 779         .resource       = vpu_resources,
 780         .num_resources  = ARRAY_SIZE(vpu_resources),
 781 };
 782
 783 /* VEU0 */
 784 static struct uio_info veu0_platform_data = {
 785         .name = "VEU0",
 786         .version = "0",
 787         .irq = intcs_evt2irq(0x700),
 788 };
 789
 790 static struct resource veu0_resources[] = {
 791         [0] = {
 792                 .name   = "VEU0",
 793                 .start  = 0xfe920000,
 794                 .end    = 0xfe9200cb,
 795                 .flags  = IORESOURCE_MEM,
 796         },
 797 };
 798
 799 static struct platform_device veu0_device = {
 800         .name           = "uio_pdrv_genirq",
 801         .id             = 1,
 802         .dev = {
 803                 .platform_data  = &veu0_platform_data,
 804         },
 805         .resource       = veu0_resources,
 806         .num_resources  = ARRAY_SIZE(veu0_resources),
 807 };
 808
 809 /* VEU1 */
 810 static struct uio_info veu1_platform_data = {
 811         .name = "VEU1",
 812         .version = "0",
 813         .irq = intcs_evt2irq(0x720),
 814 };
 815
 816 static struct resource veu1_resources[] = {
 817         [0] = {
 818                 .name   = "VEU1",
 819                 .start  = 0xfe924000,
 820                 .end    = 0xfe9240cb,
 821                 .flags  = IORESOURCE_MEM,
 822         },
 823 };
 824
 825 static struct platform_device veu1_device = {
 826         .name           = "uio_pdrv_genirq",
 827         .id             = 2,
 828         .dev = {
 829                 .platform_data  = &veu1_platform_data,
 830         },
 831         .resource       = veu1_resources,
 832         .num_resources  = ARRAY_SIZE(veu1_resources),
 833 };
 834
 835 /* VEU2 */
 836 static struct uio_info veu2_platform_data = {
 837         .name = "VEU2",
 838         .version = "0",
 839         .irq = intcs_evt2irq(0x740),
 840 };
 841
 842 static struct resource veu2_resources[] = {
 843         [0] = {
 844                 .name   = "VEU2",
 845                 .start  = 0xfe928000,
 846                 .end    = 0xfe928307,
 847                 .flags  = IORESOURCE_MEM,
 848         },
 849 };
 850
 851 static struct platform_device veu2_device = {
 852         .name           = "uio_pdrv_genirq",
 853         .id             = 3,
 854         .dev = {
 855                 .platform_data  = &veu2_platform_data,
 856         },
 857         .resource       = veu2_resources,
 858         .num_resources  = ARRAY_SIZE(veu2_resources),
 859 };
 860
 861 /* VEU3 */
 862 static struct uio_info veu3_platform_data = {
 863         .name = "VEU3",
 864         .version = "0",
 865         .irq = intcs_evt2irq(0x760),
 866 };
 867
 868 static struct resource veu3_resources[] = {
 869         [0] = {
 870                 .name   = "VEU3",
 871                 .start  = 0xfe92c000,
 872                 .end    = 0xfe92c307,
 873                 .flags  = IORESOURCE_MEM,
 874         },
 875 };
 876
 877 static struct platform_device veu3_device = {
 878         .name           = "uio_pdrv_genirq",
 879         .id             = 4,
 880         .dev = {
 881                 .platform_data  = &veu3_platform_data,
 882         },
 883         .resource       = veu3_resources,
 884         .num_resources  = ARRAY_SIZE(veu3_resources),
 885 };
 886
 887 /* JPU */
 888 static struct uio_info jpu_platform_data = {
 889         .name = "JPU",
 890         .version = "0",
 891         .irq = intcs_evt2irq(0x560),
 892 };
 893
 894 static struct resource jpu_resources[] = {
 895         [0] = {
 896                 .name   = "JPU",
 897                 .start  = 0xfe980000,
 898                 .end    = 0xfe9902d3,
 899                 .flags  = IORESOURCE_MEM,
 900         },
 901 };
 902
 903 static struct platform_device jpu_device = {
 904         .name           = "uio_pdrv_genirq",
 905         .id             = 5,
 906         .dev = {
 907                 .platform_data  = &jpu_platform_data,
 908         },
 909         .resource       = jpu_resources,
 910         .num_resources  = ARRAY_SIZE(jpu_resources),
 911 };
 912
 913 /* SPU2DSP0 */
 914 static struct uio_info spu0_platform_data = {
 915         .name = "SPU2DSP0",
 916         .version = "0",
 917         .irq = evt2irq(0x1800),
 918 };
 919
 920 static struct resource spu0_resources[] = {
 921         [0] = {
 922                 .name   = "SPU2DSP0",
 923                 .start  = 0xfe200000,
 924                 .end    = 0xfe2fffff,
 925                 .flags  = IORESOURCE_MEM,
 926         },
 927 };
 928
 929 static struct platform_device spu0_device = {
 930         .name           = "uio_pdrv_genirq",
 931         .id             = 6,
 932         .dev = {
 933                 .platform_data  = &spu0_platform_data,
 934         },
 935         .resource       = spu0_resources,
 936         .num_resources  = ARRAY_SIZE(spu0_resources),
 937 };
 938
 939 /* SPU2DSP1 */
 940 static struct uio_info spu1_platform_data = {
 941         .name = "SPU2DSP1",
 942         .version = "0",
 943         .irq = evt2irq(0x1820),
 944 };
 945
 946 static struct resource spu1_resources[] = {
 947         [0] = {
 948                 .name   = "SPU2DSP1",
 949                 .start  = 0xfe300000,
 950                 .end    = 0xfe3fffff,
 951                 .flags  = IORESOURCE_MEM,
 952         },
 953 };
 954
 955 static struct platform_device spu1_device = {
 956         .name           = "uio_pdrv_genirq",
 957         .id             = 7,
 958         .dev = {
 959                 .platform_data  = &spu1_platform_data,
 960         },
 961         .resource       = spu1_resources,
 962         .num_resources  = ARRAY_SIZE(spu1_resources),
 963 };
 964
 965 static struct platform_device *sh7372_early_devices[] __initdata = {
 966         &scif0_device,
 967         &scif1_device,
 968         &scif2_device,
 969         &scif3_device,
 970         &scif4_device,
 971         &scif5_device,
 972         &scif6_device,
 973         &cmt2_device,
 974         &tmu00_device,
 975         &tmu01_device,
 976 };
 977
 978 static struct platform_device *sh7372_late_devices[] __initdata = {
 979         &iic0_device,
 980         &iic1_device,
 981         &dma0_device,
 982         &dma1_device,
 983         &dma2_device,
 984         &usb_dma0_device,
 985         &usb_dma1_device,
 986         &vpu_device,
 987         &veu0_device,
 988         &veu1_device,
 989         &veu2_device,
 990         &veu3_device,
 991         &jpu_device,
 992         &spu0_device,
 993         &spu1_device,
 994 };
 995
 996 void __init sh7372_add_standard_devices(void)
 997 {
 998         struct pm_domain_device domain_devices[] = {
 999                 { "A3RV", &vpu_device, },
1000                 { "A4MP", &spu0_device, },
1001                 { "A4MP", &spu1_device, },
1002                 { "A3SP", &scif0_device, },
1003                 { "A3SP", &scif1_device, },
1004                 { "A3SP", &scif2_device, },
1005                 { "A3SP", &scif3_device, },
1006                 { "A3SP", &scif4_device, },
1007                 { "A3SP", &scif5_device, },
1008                 { "A3SP", &scif6_device, },
1009                 { "A3SP", &iic1_device, },
1010                 { "A3SP", &dma0_device, },
1011                 { "A3SP", &dma1_device, },
1012                 { "A3SP", &dma2_device, },
1013                 { "A3SP", &usb_dma0_device, },
1014                 { "A3SP", &usb_dma1_device, },
1015                 { "A4R", &iic0_device, },
1016                 { "A4R", &veu0_device, },
1017                 { "A4R", &veu1_device, },
1018                 { "A4R", &veu2_device, },
1019                 { "A4R", &veu3_device, },
1020                 { "A4R", &jpu_device, },
1021                 { "A4R", &tmu00_device, },
1022                 { "A4R", &tmu01_device, },
1023         };
1024
1025         sh7372_init_pm_domains();
1026
1027         platform_add_devices(sh7372_early_devices,
1028                             ARRAY_SIZE(sh7372_early_devices));
1029
1030         platform_add_devices(sh7372_late_devices,
1031                             ARRAY_SIZE(sh7372_late_devices));
1032
1033         rmobile_add_devices_to_domains(domain_devices,
1034                                        ARRAY_SIZE(domain_devices));
1035 }
1036
1037 static void __init sh7372_earlytimer_init(void)
1038 {
1039         sh7372_clock_init();
1040         shmobile_earlytimer_init();
1041 }
1042
1043 void __init sh7372_add_early_devices(void)
1044 {
1045         early_platform_add_devices(sh7372_early_devices,
1046                                    ARRAY_SIZE(sh7372_early_devices));
1047
1048         /* setup early console here as well */
1049         shmobile_setup_console();
1050
1051         /* override timer setup with soc-specific code */
1052         shmobile_timer.init = sh7372_earlytimer_init;
1053 }
1054
1055 #ifdef CONFIG_USE_OF
1056
1057 void __init sh7372_add_early_devices_dt(void)
1058 {
1059         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1060
1061         early_platform_add_devices(sh7372_early_devices,
1062                                    ARRAY_SIZE(sh7372_early_devices));
1063
1064         /* setup early console here as well */
1065         shmobile_setup_console();
1066 }
1067
1068 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1069         { }
1070 };
1071
1072 void __init sh7372_add_standard_devices_dt(void)
1073 {
1074         /* clocks are setup late during boot in the case of DT */
1075         sh7372_clock_init();
1076
1077         platform_add_devices(sh7372_early_devices,
1078                             ARRAY_SIZE(sh7372_early_devices));
1079
1080         of_platform_populate(NULL, of_default_bus_match_table,
1081                              sh7372_auxdata_lookup, NULL);
1082 }
1083
1084 static const char *sh7372_boards_compat_dt[] __initdata = {
1085         "renesas,sh7372",
1086         NULL,
1087 };
1088
1089 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1090         .map_io         = sh7372_map_io,
1091         .init_early     = sh7372_add_early_devices_dt,
1092         .nr_irqs        = NR_IRQS_LEGACY,
1093         .init_irq       = sh7372_init_irq,
1094         .handle_irq     = shmobile_handle_irq_intc,
1095         .init_machine   = sh7372_add_standard_devices_dt,
1096         .timer          = &shmobile_timer,
1097         .dt_compat      = sh7372_boards_compat_dt,
1098 MACHINE_END
1099
1100 #endif /* CONFIG_USE_OF */