2 * sh7372 processor support
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/of_platform.h>
26 #include <linux/uio_driver.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/pm_domain.h>
35 #include <linux/dma-mapping.h>
36 #include <mach/dma-register.h>
37 #include <mach/hardware.h>
38 #include <mach/irqs.h>
39 #include <mach/sh7372.h>
40 #include <mach/common.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach-types.h>
43 #include <asm/mach/arch.h>
44 #include <asm/mach/time.h>
46 static struct map_desc sh7372_io_desc[] __initdata = {
47 /* create a 1:1 entity map for 0xe6xxxxxx
48 * used by CPGA, INTC and PFC.
51 .virtual = 0xe6000000,
52 .pfn = __phys_to_pfn(0xe6000000),
54 .type = MT_DEVICE_NONSHARED
58 void __init sh7372_map_io(void)
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
64 static struct plat_sci_port scif0_platform_data = {
65 .mapbase = 0xe6c40000,
66 .flags = UPF_BOOT_AUTOCONF,
67 .scscr = SCSCR_RE | SCSCR_TE,
68 .scbrr_algo_id = SCBRR_ALGO_4,
70 .irqs = { evt2irq(0x0c00), evt2irq(0x0c00),
71 evt2irq(0x0c00), evt2irq(0x0c00) },
74 static struct platform_device scif0_device = {
78 .platform_data = &scif0_platform_data,
83 static struct plat_sci_port scif1_platform_data = {
84 .mapbase = 0xe6c50000,
85 .flags = UPF_BOOT_AUTOCONF,
86 .scscr = SCSCR_RE | SCSCR_TE,
87 .scbrr_algo_id = SCBRR_ALGO_4,
89 .irqs = { evt2irq(0x0c20), evt2irq(0x0c20),
90 evt2irq(0x0c20), evt2irq(0x0c20) },
93 static struct platform_device scif1_device = {
97 .platform_data = &scif1_platform_data,
102 static struct plat_sci_port scif2_platform_data = {
103 .mapbase = 0xe6c60000,
104 .flags = UPF_BOOT_AUTOCONF,
105 .scscr = SCSCR_RE | SCSCR_TE,
106 .scbrr_algo_id = SCBRR_ALGO_4,
108 .irqs = { evt2irq(0x0c40), evt2irq(0x0c40),
109 evt2irq(0x0c40), evt2irq(0x0c40) },
112 static struct platform_device scif2_device = {
116 .platform_data = &scif2_platform_data,
121 static struct plat_sci_port scif3_platform_data = {
122 .mapbase = 0xe6c70000,
123 .flags = UPF_BOOT_AUTOCONF,
124 .scscr = SCSCR_RE | SCSCR_TE,
125 .scbrr_algo_id = SCBRR_ALGO_4,
127 .irqs = { evt2irq(0x0c60), evt2irq(0x0c60),
128 evt2irq(0x0c60), evt2irq(0x0c60) },
131 static struct platform_device scif3_device = {
135 .platform_data = &scif3_platform_data,
140 static struct plat_sci_port scif4_platform_data = {
141 .mapbase = 0xe6c80000,
142 .flags = UPF_BOOT_AUTOCONF,
143 .scscr = SCSCR_RE | SCSCR_TE,
144 .scbrr_algo_id = SCBRR_ALGO_4,
146 .irqs = { evt2irq(0x0d20), evt2irq(0x0d20),
147 evt2irq(0x0d20), evt2irq(0x0d20) },
150 static struct platform_device scif4_device = {
154 .platform_data = &scif4_platform_data,
159 static struct plat_sci_port scif5_platform_data = {
160 .mapbase = 0xe6cb0000,
161 .flags = UPF_BOOT_AUTOCONF,
162 .scscr = SCSCR_RE | SCSCR_TE,
163 .scbrr_algo_id = SCBRR_ALGO_4,
165 .irqs = { evt2irq(0x0d40), evt2irq(0x0d40),
166 evt2irq(0x0d40), evt2irq(0x0d40) },
169 static struct platform_device scif5_device = {
173 .platform_data = &scif5_platform_data,
178 static struct plat_sci_port scif6_platform_data = {
179 .mapbase = 0xe6c30000,
180 .flags = UPF_BOOT_AUTOCONF,
181 .scscr = SCSCR_RE | SCSCR_TE,
182 .scbrr_algo_id = SCBRR_ALGO_4,
184 .irqs = { evt2irq(0x0d60), evt2irq(0x0d60),
185 evt2irq(0x0d60), evt2irq(0x0d60) },
188 static struct platform_device scif6_device = {
192 .platform_data = &scif6_platform_data,
197 static struct sh_timer_config cmt2_platform_data = {
199 .channel_offset = 0x40,
201 .clockevent_rating = 125,
202 .clocksource_rating = 125,
205 static struct resource cmt2_resources[] = {
210 .flags = IORESOURCE_MEM,
213 .start = evt2irq(0x0b80), /* CMT2 */
214 .flags = IORESOURCE_IRQ,
218 static struct platform_device cmt2_device = {
222 .platform_data = &cmt2_platform_data,
224 .resource = cmt2_resources,
225 .num_resources = ARRAY_SIZE(cmt2_resources),
229 static struct sh_timer_config tmu00_platform_data = {
231 .channel_offset = 0x4,
233 .clockevent_rating = 200,
236 static struct resource tmu00_resources[] = {
241 .flags = IORESOURCE_MEM,
244 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
245 .flags = IORESOURCE_IRQ,
249 static struct platform_device tmu00_device = {
253 .platform_data = &tmu00_platform_data,
255 .resource = tmu00_resources,
256 .num_resources = ARRAY_SIZE(tmu00_resources),
259 static struct sh_timer_config tmu01_platform_data = {
261 .channel_offset = 0x10,
263 .clocksource_rating = 200,
266 static struct resource tmu01_resources[] = {
271 .flags = IORESOURCE_MEM,
274 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
275 .flags = IORESOURCE_IRQ,
279 static struct platform_device tmu01_device = {
283 .platform_data = &tmu01_platform_data,
285 .resource = tmu01_resources,
286 .num_resources = ARRAY_SIZE(tmu01_resources),
290 static struct resource iic0_resources[] = {
294 .end = 0xFFF20425 - 1,
295 .flags = IORESOURCE_MEM,
298 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
299 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
300 .flags = IORESOURCE_IRQ,
304 static struct platform_device iic0_device = {
305 .name = "i2c-sh_mobile",
306 .id = 0, /* "i2c0" clock */
307 .num_resources = ARRAY_SIZE(iic0_resources),
308 .resource = iic0_resources,
311 static struct resource iic1_resources[] = {
315 .end = 0xE6C20425 - 1,
316 .flags = IORESOURCE_MEM,
319 .start = evt2irq(0x780), /* IIC1_ALI1 */
320 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
321 .flags = IORESOURCE_IRQ,
325 static struct platform_device iic1_device = {
326 .name = "i2c-sh_mobile",
327 .id = 1, /* "i2c1" clock */
328 .num_resources = ARRAY_SIZE(iic1_resources),
329 .resource = iic1_resources,
333 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
335 .slave_id = SHDMA_SLAVE_SCIF0_TX,
337 .chcr = CHCR_TX(XMIT_SZ_8BIT),
340 .slave_id = SHDMA_SLAVE_SCIF0_RX,
342 .chcr = CHCR_RX(XMIT_SZ_8BIT),
345 .slave_id = SHDMA_SLAVE_SCIF1_TX,
347 .chcr = CHCR_TX(XMIT_SZ_8BIT),
350 .slave_id = SHDMA_SLAVE_SCIF1_RX,
352 .chcr = CHCR_RX(XMIT_SZ_8BIT),
355 .slave_id = SHDMA_SLAVE_SCIF2_TX,
357 .chcr = CHCR_TX(XMIT_SZ_8BIT),
360 .slave_id = SHDMA_SLAVE_SCIF2_RX,
362 .chcr = CHCR_RX(XMIT_SZ_8BIT),
365 .slave_id = SHDMA_SLAVE_SCIF3_TX,
367 .chcr = CHCR_TX(XMIT_SZ_8BIT),
370 .slave_id = SHDMA_SLAVE_SCIF3_RX,
372 .chcr = CHCR_RX(XMIT_SZ_8BIT),
375 .slave_id = SHDMA_SLAVE_SCIF4_TX,
377 .chcr = CHCR_TX(XMIT_SZ_8BIT),
380 .slave_id = SHDMA_SLAVE_SCIF4_RX,
382 .chcr = CHCR_RX(XMIT_SZ_8BIT),
385 .slave_id = SHDMA_SLAVE_SCIF5_TX,
387 .chcr = CHCR_TX(XMIT_SZ_8BIT),
390 .slave_id = SHDMA_SLAVE_SCIF5_RX,
392 .chcr = CHCR_RX(XMIT_SZ_8BIT),
395 .slave_id = SHDMA_SLAVE_SCIF6_TX,
397 .chcr = CHCR_TX(XMIT_SZ_8BIT),
400 .slave_id = SHDMA_SLAVE_SCIF6_RX,
402 .chcr = CHCR_RX(XMIT_SZ_8BIT),
405 .slave_id = SHDMA_SLAVE_SDHI0_TX,
407 .chcr = CHCR_TX(XMIT_SZ_16BIT),
410 .slave_id = SHDMA_SLAVE_SDHI0_RX,
412 .chcr = CHCR_RX(XMIT_SZ_16BIT),
415 .slave_id = SHDMA_SLAVE_SDHI1_TX,
417 .chcr = CHCR_TX(XMIT_SZ_16BIT),
420 .slave_id = SHDMA_SLAVE_SDHI1_RX,
422 .chcr = CHCR_RX(XMIT_SZ_16BIT),
425 .slave_id = SHDMA_SLAVE_SDHI2_TX,
427 .chcr = CHCR_TX(XMIT_SZ_16BIT),
430 .slave_id = SHDMA_SLAVE_SDHI2_RX,
432 .chcr = CHCR_RX(XMIT_SZ_16BIT),
435 .slave_id = SHDMA_SLAVE_FSIA_TX,
437 .chcr = CHCR_TX(XMIT_SZ_32BIT),
440 .slave_id = SHDMA_SLAVE_FSIA_RX,
442 .chcr = CHCR_RX(XMIT_SZ_32BIT),
445 .slave_id = SHDMA_SLAVE_MMCIF_TX,
447 .chcr = CHCR_TX(XMIT_SZ_32BIT),
450 .slave_id = SHDMA_SLAVE_MMCIF_RX,
452 .chcr = CHCR_RX(XMIT_SZ_32BIT),
457 #define SH7372_CHCLR (0x220 - 0x20)
459 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
464 .chclr_offset = SH7372_CHCLR + 0,
469 .chclr_offset = SH7372_CHCLR + 0x10,
474 .chclr_offset = SH7372_CHCLR + 0x20,
479 .chclr_offset = SH7372_CHCLR + 0x30,
484 .chclr_offset = SH7372_CHCLR + 0x50,
489 .chclr_offset = SH7372_CHCLR + 0x60,
493 static struct sh_dmae_pdata dma_platform_data = {
494 .slave = sh7372_dmae_slaves,
495 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
496 .channel = sh7372_dmae_channels,
497 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
498 .ts_low_shift = TS_LOW_SHIFT,
499 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
500 .ts_high_shift = TS_HI_SHIFT,
501 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
502 .ts_shift = dma_ts_shift,
503 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
504 .dmaor_init = DMAOR_DME,
508 /* Resource order important! */
509 static struct resource sh7372_dmae0_resources[] = {
511 /* Channel registers and DMAOR */
514 .flags = IORESOURCE_MEM,
520 .flags = IORESOURCE_MEM,
524 .start = evt2irq(0x20c0),
525 .end = evt2irq(0x20c0),
526 .flags = IORESOURCE_IRQ,
529 /* IRQ for channels 0-5 */
530 .start = evt2irq(0x2000),
531 .end = evt2irq(0x20a0),
532 .flags = IORESOURCE_IRQ,
536 /* Resource order important! */
537 static struct resource sh7372_dmae1_resources[] = {
539 /* Channel registers and DMAOR */
542 .flags = IORESOURCE_MEM,
548 .flags = IORESOURCE_MEM,
552 .start = evt2irq(0x21c0),
553 .end = evt2irq(0x21c0),
554 .flags = IORESOURCE_IRQ,
557 /* IRQ for channels 0-5 */
558 .start = evt2irq(0x2100),
559 .end = evt2irq(0x21a0),
560 .flags = IORESOURCE_IRQ,
564 /* Resource order important! */
565 static struct resource sh7372_dmae2_resources[] = {
567 /* Channel registers and DMAOR */
570 .flags = IORESOURCE_MEM,
576 .flags = IORESOURCE_MEM,
580 .start = evt2irq(0x22c0),
581 .end = evt2irq(0x22c0),
582 .flags = IORESOURCE_IRQ,
585 /* IRQ for channels 0-5 */
586 .start = evt2irq(0x2200),
587 .end = evt2irq(0x22a0),
588 .flags = IORESOURCE_IRQ,
592 static struct platform_device dma0_device = {
593 .name = "sh-dma-engine",
595 .resource = sh7372_dmae0_resources,
596 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
598 .platform_data = &dma_platform_data,
602 static struct platform_device dma1_device = {
603 .name = "sh-dma-engine",
605 .resource = sh7372_dmae1_resources,
606 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
608 .platform_data = &dma_platform_data,
612 static struct platform_device dma2_device = {
613 .name = "sh-dma-engine",
615 .resource = sh7372_dmae2_resources,
616 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
618 .platform_data = &dma_platform_data,
625 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
634 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
636 .slave_id = SHDMA_SLAVE_USB0_TX,
637 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
639 .slave_id = SHDMA_SLAVE_USB0_RX,
640 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
644 static struct sh_dmae_pdata usb_dma0_platform_data = {
645 .slave = sh7372_usb_dmae0_slaves,
646 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
647 .channel = sh7372_usb_dmae_channels,
648 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
649 .ts_low_shift = USBTS_LOW_SHIFT,
650 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
651 .ts_high_shift = USBTS_HI_SHIFT,
652 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
653 .ts_shift = dma_usbts_shift,
654 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
655 .dmaor_init = DMAOR_DME,
657 .chcr_ie_bit = 1 << 5,
664 static struct resource sh7372_usb_dmae0_resources[] = {
666 /* Channel registers and DMAOR */
668 .end = 0xe68a0064 - 1,
669 .flags = IORESOURCE_MEM,
674 .end = 0xe68a0014 - 1,
675 .flags = IORESOURCE_MEM,
678 /* IRQ for channels */
679 .start = evt2irq(0x0a00),
680 .end = evt2irq(0x0a00),
681 .flags = IORESOURCE_IRQ,
685 static struct platform_device usb_dma0_device = {
686 .name = "sh-dma-engine",
688 .resource = sh7372_usb_dmae0_resources,
689 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
691 .platform_data = &usb_dma0_platform_data,
696 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
698 .slave_id = SHDMA_SLAVE_USB1_TX,
699 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
701 .slave_id = SHDMA_SLAVE_USB1_RX,
702 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
706 static struct sh_dmae_pdata usb_dma1_platform_data = {
707 .slave = sh7372_usb_dmae1_slaves,
708 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
709 .channel = sh7372_usb_dmae_channels,
710 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
711 .ts_low_shift = USBTS_LOW_SHIFT,
712 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
713 .ts_high_shift = USBTS_HI_SHIFT,
714 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
715 .ts_shift = dma_usbts_shift,
716 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
717 .dmaor_init = DMAOR_DME,
719 .chcr_ie_bit = 1 << 5,
726 static struct resource sh7372_usb_dmae1_resources[] = {
728 /* Channel registers and DMAOR */
730 .end = 0xe68c0064 - 1,
731 .flags = IORESOURCE_MEM,
736 .end = 0xe68c0014 - 1,
737 .flags = IORESOURCE_MEM,
740 /* IRQ for channels */
741 .start = evt2irq(0x1d00),
742 .end = evt2irq(0x1d00),
743 .flags = IORESOURCE_IRQ,
747 static struct platform_device usb_dma1_device = {
748 .name = "sh-dma-engine",
750 .resource = sh7372_usb_dmae1_resources,
751 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
753 .platform_data = &usb_dma1_platform_data,
758 static struct uio_info vpu_platform_data = {
761 .irq = intcs_evt2irq(0x980),
764 static struct resource vpu_resources[] = {
769 .flags = IORESOURCE_MEM,
773 static struct platform_device vpu_device = {
774 .name = "uio_pdrv_genirq",
777 .platform_data = &vpu_platform_data,
779 .resource = vpu_resources,
780 .num_resources = ARRAY_SIZE(vpu_resources),
784 static struct uio_info veu0_platform_data = {
787 .irq = intcs_evt2irq(0x700),
790 static struct resource veu0_resources[] = {
795 .flags = IORESOURCE_MEM,
799 static struct platform_device veu0_device = {
800 .name = "uio_pdrv_genirq",
803 .platform_data = &veu0_platform_data,
805 .resource = veu0_resources,
806 .num_resources = ARRAY_SIZE(veu0_resources),
810 static struct uio_info veu1_platform_data = {
813 .irq = intcs_evt2irq(0x720),
816 static struct resource veu1_resources[] = {
821 .flags = IORESOURCE_MEM,
825 static struct platform_device veu1_device = {
826 .name = "uio_pdrv_genirq",
829 .platform_data = &veu1_platform_data,
831 .resource = veu1_resources,
832 .num_resources = ARRAY_SIZE(veu1_resources),
836 static struct uio_info veu2_platform_data = {
839 .irq = intcs_evt2irq(0x740),
842 static struct resource veu2_resources[] = {
847 .flags = IORESOURCE_MEM,
851 static struct platform_device veu2_device = {
852 .name = "uio_pdrv_genirq",
855 .platform_data = &veu2_platform_data,
857 .resource = veu2_resources,
858 .num_resources = ARRAY_SIZE(veu2_resources),
862 static struct uio_info veu3_platform_data = {
865 .irq = intcs_evt2irq(0x760),
868 static struct resource veu3_resources[] = {
873 .flags = IORESOURCE_MEM,
877 static struct platform_device veu3_device = {
878 .name = "uio_pdrv_genirq",
881 .platform_data = &veu3_platform_data,
883 .resource = veu3_resources,
884 .num_resources = ARRAY_SIZE(veu3_resources),
888 static struct uio_info jpu_platform_data = {
891 .irq = intcs_evt2irq(0x560),
894 static struct resource jpu_resources[] = {
899 .flags = IORESOURCE_MEM,
903 static struct platform_device jpu_device = {
904 .name = "uio_pdrv_genirq",
907 .platform_data = &jpu_platform_data,
909 .resource = jpu_resources,
910 .num_resources = ARRAY_SIZE(jpu_resources),
914 static struct uio_info spu0_platform_data = {
917 .irq = evt2irq(0x1800),
920 static struct resource spu0_resources[] = {
925 .flags = IORESOURCE_MEM,
929 static struct platform_device spu0_device = {
930 .name = "uio_pdrv_genirq",
933 .platform_data = &spu0_platform_data,
935 .resource = spu0_resources,
936 .num_resources = ARRAY_SIZE(spu0_resources),
940 static struct uio_info spu1_platform_data = {
943 .irq = evt2irq(0x1820),
946 static struct resource spu1_resources[] = {
951 .flags = IORESOURCE_MEM,
955 static struct platform_device spu1_device = {
956 .name = "uio_pdrv_genirq",
959 .platform_data = &spu1_platform_data,
961 .resource = spu1_resources,
962 .num_resources = ARRAY_SIZE(spu1_resources),
965 static struct platform_device *sh7372_early_devices[] __initdata = {
978 static struct platform_device *sh7372_late_devices[] __initdata = {
996 void __init sh7372_add_standard_devices(void)
998 struct pm_domain_device domain_devices[] = {
999 { "A3RV", &vpu_device, },
1000 { "A4MP", &spu0_device, },
1001 { "A4MP", &spu1_device, },
1002 { "A3SP", &scif0_device, },
1003 { "A3SP", &scif1_device, },
1004 { "A3SP", &scif2_device, },
1005 { "A3SP", &scif3_device, },
1006 { "A3SP", &scif4_device, },
1007 { "A3SP", &scif5_device, },
1008 { "A3SP", &scif6_device, },
1009 { "A3SP", &iic1_device, },
1010 { "A3SP", &dma0_device, },
1011 { "A3SP", &dma1_device, },
1012 { "A3SP", &dma2_device, },
1013 { "A3SP", &usb_dma0_device, },
1014 { "A3SP", &usb_dma1_device, },
1015 { "A4R", &iic0_device, },
1016 { "A4R", &veu0_device, },
1017 { "A4R", &veu1_device, },
1018 { "A4R", &veu2_device, },
1019 { "A4R", &veu3_device, },
1020 { "A4R", &jpu_device, },
1021 { "A4R", &tmu00_device, },
1022 { "A4R", &tmu01_device, },
1025 sh7372_init_pm_domains();
1027 platform_add_devices(sh7372_early_devices,
1028 ARRAY_SIZE(sh7372_early_devices));
1030 platform_add_devices(sh7372_late_devices,
1031 ARRAY_SIZE(sh7372_late_devices));
1033 rmobile_add_devices_to_domains(domain_devices,
1034 ARRAY_SIZE(domain_devices));
1037 static void __init sh7372_earlytimer_init(void)
1039 sh7372_clock_init();
1040 shmobile_earlytimer_init();
1043 void __init sh7372_add_early_devices(void)
1045 early_platform_add_devices(sh7372_early_devices,
1046 ARRAY_SIZE(sh7372_early_devices));
1048 /* setup early console here as well */
1049 shmobile_setup_console();
1051 /* override timer setup with soc-specific code */
1052 shmobile_timer.init = sh7372_earlytimer_init;
1055 #ifdef CONFIG_USE_OF
1057 void __init sh7372_add_early_devices_dt(void)
1059 shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
1061 early_platform_add_devices(sh7372_early_devices,
1062 ARRAY_SIZE(sh7372_early_devices));
1064 /* setup early console here as well */
1065 shmobile_setup_console();
1068 static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1072 void __init sh7372_add_standard_devices_dt(void)
1074 /* clocks are setup late during boot in the case of DT */
1075 sh7372_clock_init();
1077 platform_add_devices(sh7372_early_devices,
1078 ARRAY_SIZE(sh7372_early_devices));
1080 of_platform_populate(NULL, of_default_bus_match_table,
1081 sh7372_auxdata_lookup, NULL);
1084 static const char *sh7372_boards_compat_dt[] __initdata = {
1089 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1090 .map_io = sh7372_map_io,
1091 .init_early = sh7372_add_early_devices_dt,
1092 .nr_irqs = NR_IRQS_LEGACY,
1093 .init_irq = sh7372_init_irq,
1094 .handle_irq = shmobile_handle_irq_intc,
1095 .init_machine = sh7372_add_standard_devices_dt,
1096 .timer = &shmobile_timer,
1097 .dt_compat = sh7372_boards_compat_dt,
1100 #endif /* CONFIG_USE_OF */