arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/uio_driver.h>
  27 #include <linux/delay.h>
  28 #include <linux/input.h>
  29 #include <linux/io.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/pm_domain.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/platform_data/sh_ipmmu.h>
  36
  37 #include <asm/mach/map.h>
  38 #include <asm/mach-types.h>
  39 #include <asm/mach/arch.h>
  40 #include <asm/mach/time.h>
  41
  42 #include "common.h"
  43 #include "dma-register.h"
  44 #include "irqs.h"
  45 #include "pm-rmobile.h"
  46 #include "sh7372.h"
  47
  48 static struct map_desc sh7372_io_desc[] __initdata = {
  49         /* create a 1:1 entity map for 0xe6xxxxxx
  50          * used by CPGA, INTC and PFC.
  51          */
  52         {
  53                 .virtual        = 0xe6000000,
  54                 .pfn            = __phys_to_pfn(0xe6000000),
  55                 .length         = 256 << 20,
  56                 .type           = MT_DEVICE_NONSHARED
  57         },
  58 };
  59
  60 void __init sh7372_map_io(void)
  61 {
  62         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
  63 }
  64
  65 /* PFC */
  66 static struct resource sh7372_pfc_resources[] = {
  67         [0] = {
  68                 .start  = 0xe6050000,
  69                 .end    = 0xe6057fff,
  70                 .flags  = IORESOURCE_MEM,
  71         },
  72         [1] = {
  73                 .start  = 0xe605800c,
  74                 .end    = 0xe6058027,
  75                 .flags  = IORESOURCE_MEM,
  76         }
  77 };
  78
  79 static struct platform_device sh7372_pfc_device = {
  80         .name           = "pfc-sh7372",
  81         .id             = -1,
  82         .resource       = sh7372_pfc_resources,
  83         .num_resources  = ARRAY_SIZE(sh7372_pfc_resources),
  84 };
  85
  86 void __init sh7372_pinmux_init(void)
  87 {
  88         platform_device_register(&sh7372_pfc_device);
  89 }
  90
  91 /* SCIF */
  92 #define SH7372_SCIF(scif_type, index, baseaddr, irq)            \
  93 static struct plat_sci_port scif##index##_platform_data = {     \
  94         .type           = scif_type,                            \
  95         .flags          = UPF_BOOT_AUTOCONF,                    \
  96         .scscr          = SCSCR_RE | SCSCR_TE,                  \
  97 };                                                              \
  98                                                                 \
  99 static struct resource scif##index##_resources[] = {            \
 100         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 101         DEFINE_RES_IRQ(irq),                                    \
 102 };                                                              \
 103                                                                 \
 104 static struct platform_device scif##index##_device = {          \
 105         .name           = "sh-sci",                             \
 106         .id             = index,                                \
 107         .resource       = scif##index##_resources,              \
 108         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 109         .dev            = {                                     \
 110                 .platform_data  = &scif##index##_platform_data, \
 111         },                                                      \
 112 }
 113
 114 SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
 115 SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
 116 SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
 117 SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
 118 SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
 119 SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
 120 SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 121
 122 /* CMT */
 123 static struct sh_timer_config cmt2_platform_data = {
 124         .channels_mask = 0x20,
 125 };
 126
 127 static struct resource cmt2_resources[] = {
 128         DEFINE_RES_MEM(0xe6130000, 0x50),
 129         DEFINE_RES_IRQ(evt2irq(0x0b80)),
 130 };
 131
 132 static struct platform_device cmt2_device = {
 133         .name           = "sh-cmt-32-fast",
 134         .id             = 2,
 135         .dev = {
 136                 .platform_data  = &cmt2_platform_data,
 137         },
 138         .resource       = cmt2_resources,
 139         .num_resources  = ARRAY_SIZE(cmt2_resources),
 140 };
 141
 142 /* TMU */
 143 static struct sh_timer_config tmu0_platform_data = {
 144         .channels_mask = 7,
 145 };
 146
 147 static struct resource tmu0_resources[] = {
 148         DEFINE_RES_MEM(0xfff60000, 0x2c),
 149         DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
 150         DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
 151         DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
 152 };
 153
 154 static struct platform_device tmu0_device = {
 155         .name           = "sh-tmu",
 156         .id             = 0,
 157         .dev = {
 158                 .platform_data  = &tmu0_platform_data,
 159         },
 160         .resource       = tmu0_resources,
 161         .num_resources  = ARRAY_SIZE(tmu0_resources),
 162 };
 163
 164 /* I2C */
 165 static struct resource iic0_resources[] = {
 166         [0] = {
 167                 .name   = "IIC0",
 168                 .start  = 0xFFF20000,
 169                 .end    = 0xFFF20425 - 1,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         [1] = {
 173                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 174                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 175                 .flags  = IORESOURCE_IRQ,
 176         },
 177 };
 178
 179 static struct platform_device iic0_device = {
 180         .name           = "i2c-sh_mobile",
 181         .id             = 0, /* "i2c0" clock */
 182         .num_resources  = ARRAY_SIZE(iic0_resources),
 183         .resource       = iic0_resources,
 184 };
 185
 186 static struct resource iic1_resources[] = {
 187         [0] = {
 188                 .name   = "IIC1",
 189                 .start  = 0xE6C20000,
 190                 .end    = 0xE6C20425 - 1,
 191                 .flags  = IORESOURCE_MEM,
 192         },
 193         [1] = {
 194                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 195                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 196                 .flags  = IORESOURCE_IRQ,
 197         },
 198 };
 199
 200 static struct platform_device iic1_device = {
 201         .name           = "i2c-sh_mobile",
 202         .id             = 1, /* "i2c1" clock */
 203         .num_resources  = ARRAY_SIZE(iic1_resources),
 204         .resource       = iic1_resources,
 205 };
 206
 207 /* DMA */
 208 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 209         {
 210                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 211                 .addr           = 0xe6c40020,
 212                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 213                 .mid_rid        = 0x21,
 214         }, {
 215                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 216                 .addr           = 0xe6c40024,
 217                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 218                 .mid_rid        = 0x22,
 219         }, {
 220                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 221                 .addr           = 0xe6c50020,
 222                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 223                 .mid_rid        = 0x25,
 224         }, {
 225                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 226                 .addr           = 0xe6c50024,
 227                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 228                 .mid_rid        = 0x26,
 229         }, {
 230                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 231                 .addr           = 0xe6c60020,
 232                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 233                 .mid_rid        = 0x29,
 234         }, {
 235                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 236                 .addr           = 0xe6c60024,
 237                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 238                 .mid_rid        = 0x2a,
 239         }, {
 240                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 241                 .addr           = 0xe6c70020,
 242                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 243                 .mid_rid        = 0x2d,
 244         }, {
 245                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 246                 .addr           = 0xe6c70024,
 247                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 248                 .mid_rid        = 0x2e,
 249         }, {
 250                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 251                 .addr           = 0xe6c80020,
 252                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 253                 .mid_rid        = 0x39,
 254         }, {
 255                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 256                 .addr           = 0xe6c80024,
 257                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 258                 .mid_rid        = 0x3a,
 259         }, {
 260                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 261                 .addr           = 0xe6cb0020,
 262                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 263                 .mid_rid        = 0x35,
 264         }, {
 265                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 266                 .addr           = 0xe6cb0024,
 267                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 268                 .mid_rid        = 0x36,
 269         }, {
 270                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 271                 .addr           = 0xe6c30040,
 272                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 273                 .mid_rid        = 0x3d,
 274         }, {
 275                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 276                 .addr           = 0xe6c30060,
 277                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 278                 .mid_rid        = 0x3e,
 279         }, {
 280                 .slave_id       = SHDMA_SLAVE_FLCTL0_TX,
 281                 .addr           = 0xe6a30050,
 282                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 283                 .mid_rid        = 0x83,
 284         }, {
 285                 .slave_id       = SHDMA_SLAVE_FLCTL0_RX,
 286                 .addr           = 0xe6a30050,
 287                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 288                 .mid_rid        = 0x83,
 289         }, {
 290                 .slave_id       = SHDMA_SLAVE_FLCTL1_TX,
 291                 .addr           = 0xe6a30060,
 292                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 293                 .mid_rid        = 0x87,
 294         }, {
 295                 .slave_id       = SHDMA_SLAVE_FLCTL1_RX,
 296                 .addr           = 0xe6a30060,
 297                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 298                 .mid_rid        = 0x87,
 299         }, {
 300                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 301                 .addr           = 0xe6850030,
 302                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 303                 .mid_rid        = 0xc1,
 304         }, {
 305                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 306                 .addr           = 0xe6850030,
 307                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 308                 .mid_rid        = 0xc2,
 309         }, {
 310                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 311                 .addr           = 0xe6860030,
 312                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 313                 .mid_rid        = 0xc9,
 314         }, {
 315                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 316                 .addr           = 0xe6860030,
 317                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 318                 .mid_rid        = 0xca,
 319         }, {
 320                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 321                 .addr           = 0xe6870030,
 322                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 323                 .mid_rid        = 0xcd,
 324         }, {
 325                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 326                 .addr           = 0xe6870030,
 327                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 328                 .mid_rid        = 0xce,
 329         }, {
 330                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 331                 .addr           = 0xfe1f0024,
 332                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 333                 .mid_rid        = 0xb1,
 334         }, {
 335                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 336                 .addr           = 0xfe1f0020,
 337                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 338                 .mid_rid        = 0xb2,
 339         }, {
 340                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 341                 .addr           = 0xe6bd0034,
 342                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 343                 .mid_rid        = 0xd1,
 344         }, {
 345                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 346                 .addr           = 0xe6bd0034,
 347                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 348                 .mid_rid        = 0xd2,
 349         },
 350 };
 351
 352 #define SH7372_CHCLR (0x220 - 0x20)
 353
 354 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 355         {
 356                 .offset = 0,
 357                 .dmars = 0,
 358                 .dmars_bit = 0,
 359                 .chclr_offset = SH7372_CHCLR + 0,
 360         }, {
 361                 .offset = 0x10,
 362                 .dmars = 0,
 363                 .dmars_bit = 8,
 364                 .chclr_offset = SH7372_CHCLR + 0x10,
 365         }, {
 366                 .offset = 0x20,
 367                 .dmars = 4,
 368                 .dmars_bit = 0,
 369                 .chclr_offset = SH7372_CHCLR + 0x20,
 370         }, {
 371                 .offset = 0x30,
 372                 .dmars = 4,
 373                 .dmars_bit = 8,
 374                 .chclr_offset = SH7372_CHCLR + 0x30,
 375         }, {
 376                 .offset = 0x50,
 377                 .dmars = 8,
 378                 .dmars_bit = 0,
 379                 .chclr_offset = SH7372_CHCLR + 0x50,
 380         }, {
 381                 .offset = 0x60,
 382                 .dmars = 8,
 383                 .dmars_bit = 8,
 384                 .chclr_offset = SH7372_CHCLR + 0x60,
 385         }
 386 };
 387
 388 static struct sh_dmae_pdata dma_platform_data = {
 389         .slave          = sh7372_dmae_slaves,
 390         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 391         .channel        = sh7372_dmae_channels,
 392         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 393         .ts_low_shift   = TS_LOW_SHIFT,
 394         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 395         .ts_high_shift  = TS_HI_SHIFT,
 396         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 397         .ts_shift       = dma_ts_shift,
 398         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 399         .dmaor_init     = DMAOR_DME,
 400         .chclr_present  = 1,
 401 };
 402
 403 /* Resource order important! */
 404 static struct resource sh7372_dmae0_resources[] = {
 405         {
 406                 /* Channel registers and DMAOR */
 407                 .start  = 0xfe008020,
 408                 .end    = 0xfe00828f,
 409                 .flags  = IORESOURCE_MEM,
 410         },
 411         {
 412                 /* DMARSx */
 413                 .start  = 0xfe009000,
 414                 .end    = 0xfe00900b,
 415                 .flags  = IORESOURCE_MEM,
 416         },
 417         {
 418                 .name   = "error_irq",
 419                 .start  = evt2irq(0x20c0),
 420                 .end    = evt2irq(0x20c0),
 421                 .flags  = IORESOURCE_IRQ,
 422         },
 423         {
 424                 /* IRQ for channels 0-5 */
 425                 .start  = evt2irq(0x2000),
 426                 .end    = evt2irq(0x20a0),
 427                 .flags  = IORESOURCE_IRQ,
 428         },
 429 };
 430
 431 /* Resource order important! */
 432 static struct resource sh7372_dmae1_resources[] = {
 433         {
 434                 /* Channel registers and DMAOR */
 435                 .start  = 0xfe018020,
 436                 .end    = 0xfe01828f,
 437                 .flags  = IORESOURCE_MEM,
 438         },
 439         {
 440                 /* DMARSx */
 441                 .start  = 0xfe019000,
 442                 .end    = 0xfe01900b,
 443                 .flags  = IORESOURCE_MEM,
 444         },
 445         {
 446                 .name   = "error_irq",
 447                 .start  = evt2irq(0x21c0),
 448                 .end    = evt2irq(0x21c0),
 449                 .flags  = IORESOURCE_IRQ,
 450         },
 451         {
 452                 /* IRQ for channels 0-5 */
 453                 .start  = evt2irq(0x2100),
 454                 .end    = evt2irq(0x21a0),
 455                 .flags  = IORESOURCE_IRQ,
 456         },
 457 };
 458
 459 /* Resource order important! */
 460 static struct resource sh7372_dmae2_resources[] = {
 461         {
 462                 /* Channel registers and DMAOR */
 463                 .start  = 0xfe028020,
 464                 .end    = 0xfe02828f,
 465                 .flags  = IORESOURCE_MEM,
 466         },
 467         {
 468                 /* DMARSx */
 469                 .start  = 0xfe029000,
 470                 .end    = 0xfe02900b,
 471                 .flags  = IORESOURCE_MEM,
 472         },
 473         {
 474                 .name   = "error_irq",
 475                 .start  = evt2irq(0x22c0),
 476                 .end    = evt2irq(0x22c0),
 477                 .flags  = IORESOURCE_IRQ,
 478         },
 479         {
 480                 /* IRQ for channels 0-5 */
 481                 .start  = evt2irq(0x2200),
 482                 .end    = evt2irq(0x22a0),
 483                 .flags  = IORESOURCE_IRQ,
 484         },
 485 };
 486
 487 static struct platform_device dma0_device = {
 488         .name           = "sh-dma-engine",
 489         .id             = 0,
 490         .resource       = sh7372_dmae0_resources,
 491         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 492         .dev            = {
 493                 .platform_data  = &dma_platform_data,
 494         },
 495 };
 496
 497 static struct platform_device dma1_device = {
 498         .name           = "sh-dma-engine",
 499         .id             = 1,
 500         .resource       = sh7372_dmae1_resources,
 501         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 502         .dev            = {
 503                 .platform_data  = &dma_platform_data,
 504         },
 505 };
 506
 507 static struct platform_device dma2_device = {
 508         .name           = "sh-dma-engine",
 509         .id             = 2,
 510         .resource       = sh7372_dmae2_resources,
 511         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 512         .dev            = {
 513                 .platform_data  = &dma_platform_data,
 514         },
 515 };
 516
 517 /*
 518  * USB-DMAC
 519  */
 520 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 521         {
 522                 .offset = 0,
 523         }, {
 524                 .offset = 0x20,
 525         },
 526 };
 527
 528 /* USB DMAC0 */
 529 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
 530         {
 531                 .slave_id       = SHDMA_SLAVE_USB0_TX,
 532                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 533         }, {
 534                 .slave_id       = SHDMA_SLAVE_USB0_RX,
 535                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 536         },
 537 };
 538
 539 static struct sh_dmae_pdata usb_dma0_platform_data = {
 540         .slave          = sh7372_usb_dmae0_slaves,
 541         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
 542         .channel        = sh7372_usb_dmae_channels,
 543         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 544         .ts_low_shift   = USBTS_LOW_SHIFT,
 545         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 546         .ts_high_shift  = USBTS_HI_SHIFT,
 547         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 548         .ts_shift       = dma_usbts_shift,
 549         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 550         .dmaor_init     = DMAOR_DME,
 551         .chcr_offset    = 0x14,
 552         .chcr_ie_bit    = 1 << 5,
 553         .dmaor_is_32bit = 1,
 554         .needs_tend_set = 1,
 555         .no_dmars       = 1,
 556         .slave_only     = 1,
 557 };
 558
 559 static struct resource sh7372_usb_dmae0_resources[] = {
 560         {
 561                 /* Channel registers and DMAOR */
 562                 .start  = 0xe68a0020,
 563                 .end    = 0xe68a0064 - 1,
 564                 .flags  = IORESOURCE_MEM,
 565         },
 566         {
 567                 /* VCR/SWR/DMICR */
 568                 .start  = 0xe68a0000,
 569                 .end    = 0xe68a0014 - 1,
 570                 .flags  = IORESOURCE_MEM,
 571         },
 572         {
 573                 /* IRQ for channels */
 574                 .start  = evt2irq(0x0a00),
 575                 .end    = evt2irq(0x0a00),
 576                 .flags  = IORESOURCE_IRQ,
 577         },
 578 };
 579
 580 static struct platform_device usb_dma0_device = {
 581         .name           = "sh-dma-engine",
 582         .id             = 3,
 583         .resource       = sh7372_usb_dmae0_resources,
 584         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
 585         .dev            = {
 586                 .platform_data  = &usb_dma0_platform_data,
 587         },
 588 };
 589
 590 /* USB DMAC1 */
 591 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
 592         {
 593                 .slave_id       = SHDMA_SLAVE_USB1_TX,
 594                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 595         }, {
 596                 .slave_id       = SHDMA_SLAVE_USB1_RX,
 597                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 598         },
 599 };
 600
 601 static struct sh_dmae_pdata usb_dma1_platform_data = {
 602         .slave          = sh7372_usb_dmae1_slaves,
 603         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
 604         .channel        = sh7372_usb_dmae_channels,
 605         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
 606         .ts_low_shift   = USBTS_LOW_SHIFT,
 607         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 608         .ts_high_shift  = USBTS_HI_SHIFT,
 609         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 610         .ts_shift       = dma_usbts_shift,
 611         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 612         .dmaor_init     = DMAOR_DME,
 613         .chcr_offset    = 0x14,
 614         .chcr_ie_bit    = 1 << 5,
 615         .dmaor_is_32bit = 1,
 616         .needs_tend_set = 1,
 617         .no_dmars       = 1,
 618         .slave_only     = 1,
 619 };
 620
 621 static struct resource sh7372_usb_dmae1_resources[] = {
 622         {
 623                 /* Channel registers and DMAOR */
 624                 .start  = 0xe68c0020,
 625                 .end    = 0xe68c0064 - 1,
 626                 .flags  = IORESOURCE_MEM,
 627         },
 628         {
 629                 /* VCR/SWR/DMICR */
 630                 .start  = 0xe68c0000,
 631                 .end    = 0xe68c0014 - 1,
 632                 .flags  = IORESOURCE_MEM,
 633         },
 634         {
 635                 /* IRQ for channels */
 636                 .start  = evt2irq(0x1d00),
 637                 .end    = evt2irq(0x1d00),
 638                 .flags  = IORESOURCE_IRQ,
 639         },
 640 };
 641
 642 static struct platform_device usb_dma1_device = {
 643         .name           = "sh-dma-engine",
 644         .id             = 4,
 645         .resource       = sh7372_usb_dmae1_resources,
 646         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
 647         .dev            = {
 648                 .platform_data  = &usb_dma1_platform_data,
 649         },
 650 };
 651
 652 /* VPU */
 653 static struct uio_info vpu_platform_data = {
 654         .name = "VPU5HG",
 655         .version = "0",
 656         .irq = intcs_evt2irq(0x980),
 657 };
 658
 659 static struct resource vpu_resources[] = {
 660         [0] = {
 661                 .name   = "VPU",
 662                 .start  = 0xfe900000,
 663                 .end    = 0xfe900157,
 664                 .flags  = IORESOURCE_MEM,
 665         },
 666 };
 667
 668 static struct platform_device vpu_device = {
 669         .name           = "uio_pdrv_genirq",
 670         .id             = 0,
 671         .dev = {
 672                 .platform_data  = &vpu_platform_data,
 673         },
 674         .resource       = vpu_resources,
 675         .num_resources  = ARRAY_SIZE(vpu_resources),
 676 };
 677
 678 /* VEU0 */
 679 static struct uio_info veu0_platform_data = {
 680         .name = "VEU0",
 681         .version = "0",
 682         .irq = intcs_evt2irq(0x700),
 683 };
 684
 685 static struct resource veu0_resources[] = {
 686         [0] = {
 687                 .name   = "VEU0",
 688                 .start  = 0xfe920000,
 689                 .end    = 0xfe9200cb,
 690                 .flags  = IORESOURCE_MEM,
 691         },
 692 };
 693
 694 static struct platform_device veu0_device = {
 695         .name           = "uio_pdrv_genirq",
 696         .id             = 1,
 697         .dev = {
 698                 .platform_data  = &veu0_platform_data,
 699         },
 700         .resource       = veu0_resources,
 701         .num_resources  = ARRAY_SIZE(veu0_resources),
 702 };
 703
 704 /* VEU1 */
 705 static struct uio_info veu1_platform_data = {
 706         .name = "VEU1",
 707         .version = "0",
 708         .irq = intcs_evt2irq(0x720),
 709 };
 710
 711 static struct resource veu1_resources[] = {
 712         [0] = {
 713                 .name   = "VEU1",
 714                 .start  = 0xfe924000,
 715                 .end    = 0xfe9240cb,
 716                 .flags  = IORESOURCE_MEM,
 717         },
 718 };
 719
 720 static struct platform_device veu1_device = {
 721         .name           = "uio_pdrv_genirq",
 722         .id             = 2,
 723         .dev = {
 724                 .platform_data  = &veu1_platform_data,
 725         },
 726         .resource       = veu1_resources,
 727         .num_resources  = ARRAY_SIZE(veu1_resources),
 728 };
 729
 730 /* VEU2 */
 731 static struct uio_info veu2_platform_data = {
 732         .name = "VEU2",
 733         .version = "0",
 734         .irq = intcs_evt2irq(0x740),
 735 };
 736
 737 static struct resource veu2_resources[] = {
 738         [0] = {
 739                 .name   = "VEU2",
 740                 .start  = 0xfe928000,
 741                 .end    = 0xfe928307,
 742                 .flags  = IORESOURCE_MEM,
 743         },
 744 };
 745
 746 static struct platform_device veu2_device = {
 747         .name           = "uio_pdrv_genirq",
 748         .id             = 3,
 749         .dev = {
 750                 .platform_data  = &veu2_platform_data,
 751         },
 752         .resource       = veu2_resources,
 753         .num_resources  = ARRAY_SIZE(veu2_resources),
 754 };
 755
 756 /* VEU3 */
 757 static struct uio_info veu3_platform_data = {
 758         .name = "VEU3",
 759         .version = "0",
 760         .irq = intcs_evt2irq(0x760),
 761 };
 762
 763 static struct resource veu3_resources[] = {
 764         [0] = {
 765                 .name   = "VEU3",
 766                 .start  = 0xfe92c000,
 767                 .end    = 0xfe92c307,
 768                 .flags  = IORESOURCE_MEM,
 769         },
 770 };
 771
 772 static struct platform_device veu3_device = {
 773         .name           = "uio_pdrv_genirq",
 774         .id             = 4,
 775         .dev = {
 776                 .platform_data  = &veu3_platform_data,
 777         },
 778         .resource       = veu3_resources,
 779         .num_resources  = ARRAY_SIZE(veu3_resources),
 780 };
 781
 782 /* JPU */
 783 static struct uio_info jpu_platform_data = {
 784         .name = "JPU",
 785         .version = "0",
 786         .irq = intcs_evt2irq(0x560),
 787 };
 788
 789 static struct resource jpu_resources[] = {
 790         [0] = {
 791                 .name   = "JPU",
 792                 .start  = 0xfe980000,
 793                 .end    = 0xfe9902d3,
 794                 .flags  = IORESOURCE_MEM,
 795         },
 796 };
 797
 798 static struct platform_device jpu_device = {
 799         .name           = "uio_pdrv_genirq",
 800         .id             = 5,
 801         .dev = {
 802                 .platform_data  = &jpu_platform_data,
 803         },
 804         .resource       = jpu_resources,
 805         .num_resources  = ARRAY_SIZE(jpu_resources),
 806 };
 807
 808 /* SPU2DSP0 */
 809 static struct uio_info spu0_platform_data = {
 810         .name = "SPU2DSP0",
 811         .version = "0",
 812         .irq = evt2irq(0x1800),
 813 };
 814
 815 static struct resource spu0_resources[] = {
 816         [0] = {
 817                 .name   = "SPU2DSP0",
 818                 .start  = 0xfe200000,
 819                 .end    = 0xfe2fffff,
 820                 .flags  = IORESOURCE_MEM,
 821         },
 822 };
 823
 824 static struct platform_device spu0_device = {
 825         .name           = "uio_pdrv_genirq",
 826         .id             = 6,
 827         .dev = {
 828                 .platform_data  = &spu0_platform_data,
 829         },
 830         .resource       = spu0_resources,
 831         .num_resources  = ARRAY_SIZE(spu0_resources),
 832 };
 833
 834 /* SPU2DSP1 */
 835 static struct uio_info spu1_platform_data = {
 836         .name = "SPU2DSP1",
 837         .version = "0",
 838         .irq = evt2irq(0x1820),
 839 };
 840
 841 static struct resource spu1_resources[] = {
 842         [0] = {
 843                 .name   = "SPU2DSP1",
 844                 .start  = 0xfe300000,
 845                 .end    = 0xfe3fffff,
 846                 .flags  = IORESOURCE_MEM,
 847         },
 848 };
 849
 850 static struct platform_device spu1_device = {
 851         .name           = "uio_pdrv_genirq",
 852         .id             = 7,
 853         .dev = {
 854                 .platform_data  = &spu1_platform_data,
 855         },
 856         .resource       = spu1_resources,
 857         .num_resources  = ARRAY_SIZE(spu1_resources),
 858 };
 859
 860 /* IPMMUI (an IPMMU module for ICB/LMB) */
 861 static struct resource ipmmu_resources[] = {
 862         [0] = {
 863                 .name   = "IPMMUI",
 864                 .start  = 0xfe951000,
 865                 .end    = 0xfe9510ff,
 866                 .flags  = IORESOURCE_MEM,
 867         },
 868 };
 869
 870 static const char * const ipmmu_dev_names[] = {
 871         "sh_mobile_lcdc_fb.0",
 872         "sh_mobile_lcdc_fb.1",
 873         "sh_mobile_ceu.0",
 874         "uio_pdrv_genirq.0",
 875         "uio_pdrv_genirq.1",
 876         "uio_pdrv_genirq.2",
 877         "uio_pdrv_genirq.3",
 878         "uio_pdrv_genirq.4",
 879         "uio_pdrv_genirq.5",
 880 };
 881
 882 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 883         .dev_names = ipmmu_dev_names,
 884         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 885 };
 886
 887 static struct platform_device ipmmu_device = {
 888         .name           = "ipmmu",
 889         .id             = -1,
 890         .dev = {
 891                 .platform_data = &ipmmu_platform_data,
 892         },
 893         .resource       = ipmmu_resources,
 894         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 895 };
 896
 897 static struct platform_device *sh7372_early_devices[] __initdata = {
 898         &scif0_device,
 899         &scif1_device,
 900         &scif2_device,
 901         &scif3_device,
 902         &scif4_device,
 903         &scif5_device,
 904         &scif6_device,
 905         &cmt2_device,
 906         &tmu0_device,
 907         &ipmmu_device,
 908 };
 909
 910 static struct platform_device *sh7372_late_devices[] __initdata = {
 911         &iic0_device,
 912         &iic1_device,
 913         &dma0_device,
 914         &dma1_device,
 915         &dma2_device,
 916         &usb_dma0_device,
 917         &usb_dma1_device,
 918         &vpu_device,
 919         &veu0_device,
 920         &veu1_device,
 921         &veu2_device,
 922         &veu3_device,
 923         &jpu_device,
 924         &spu0_device,
 925         &spu1_device,
 926 };
 927
 928 void __init sh7372_add_standard_devices(void)
 929 {
 930         struct pm_domain_device domain_devices[] = {
 931                 { "A3RV", &vpu_device, },
 932                 { "A4MP", &spu0_device, },
 933                 { "A4MP", &spu1_device, },
 934                 { "A3SP", &scif0_device, },
 935                 { "A3SP", &scif1_device, },
 936                 { "A3SP", &scif2_device, },
 937                 { "A3SP", &scif3_device, },
 938                 { "A3SP", &scif4_device, },
 939                 { "A3SP", &scif5_device, },
 940                 { "A3SP", &scif6_device, },
 941                 { "A3SP", &iic1_device, },
 942                 { "A3SP", &dma0_device, },
 943                 { "A3SP", &dma1_device, },
 944                 { "A3SP", &dma2_device, },
 945                 { "A3SP", &usb_dma0_device, },
 946                 { "A3SP", &usb_dma1_device, },
 947                 { "A4R", &iic0_device, },
 948                 { "A4R", &veu0_device, },
 949                 { "A4R", &veu1_device, },
 950                 { "A4R", &veu2_device, },
 951                 { "A4R", &veu3_device, },
 952                 { "A4R", &jpu_device, },
 953                 { "A4R", &tmu0_device, },
 954         };
 955
 956         sh7372_init_pm_domains();
 957
 958         platform_add_devices(sh7372_early_devices,
 959                             ARRAY_SIZE(sh7372_early_devices));
 960
 961         platform_add_devices(sh7372_late_devices,
 962                             ARRAY_SIZE(sh7372_late_devices));
 963
 964         rmobile_add_devices_to_domains(domain_devices,
 965                                        ARRAY_SIZE(domain_devices));
 966 }
 967
 968 void __init sh7372_earlytimer_init(void)
 969 {
 970         sh7372_clock_init();
 971         shmobile_earlytimer_init();
 972 }
 973
 974 void __init sh7372_add_early_devices(void)
 975 {
 976         early_platform_add_devices(sh7372_early_devices,
 977                                    ARRAY_SIZE(sh7372_early_devices));
 978
 979         /* setup early console here as well */
 980         shmobile_setup_console();
 981 }
 982
 983 #ifdef CONFIG_USE_OF
 984
 985 void __init sh7372_add_early_devices_dt(void)
 986 {
 987         shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
 988
 989         sh7372_add_early_devices();
 990 }
 991
 992 void __init sh7372_add_standard_devices_dt(void)
 993 {
 994         /* clocks are setup late during boot in the case of DT */
 995         sh7372_clock_init();
 996
 997         platform_add_devices(sh7372_early_devices,
 998                             ARRAY_SIZE(sh7372_early_devices));
 999
1000         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1001 }
1002
1003 static const char *sh7372_boards_compat_dt[] __initdata = {
1004         "renesas,sh7372",
1005         NULL,
1006 };
1007
1008 DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1009         .map_io         = sh7372_map_io,
1010         .init_early     = sh7372_add_early_devices_dt,
1011         .nr_irqs        = NR_IRQS_LEGACY,
1012         .init_irq       = sh7372_init_irq,
1013         .handle_irq     = shmobile_handle_irq_intc,
1014         .init_machine   = sh7372_add_standard_devices_dt,
1015         .dt_compat      = sh7372_boards_compat_dt,
1016 MACHINE_END
1017
1018 #endif /* CONFIG_USE_OF */