arch/arm/mach-shmobile/setup-r8a7791.c

   1 /*
   2  * r8a7791 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/irq.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_data/gpio-rcar.h>
  26 #include <linux/platform_data/irq-renesas-irqc.h>
  27 #include <linux/serial_sci.h>
  28 #include <linux/sh_timer.h>
  29 #include <mach/common.h>
  30 #include <mach/irqs.h>
  31 #include <mach/r8a7791.h>
  32 #include <mach/rcar-gen2.h>
  33 #include <asm/mach/arch.h>
  34
  35 static const struct resource pfc_resources[] __initconst = {
  36         DEFINE_RES_MEM(0xe6060000, 0x250),
  37 };
  38
  39 #define r8a7791_register_pfc()                                          \
  40         platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \
  41                                         ARRAY_SIZE(pfc_resources))
  42
  43 #define R8A7791_GPIO(idx, base, nr)                                     \
  44 static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \
  45         DEFINE_RES_MEM((base), 0x50),                                   \
  46         DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
  47 };                                                                      \
  48                                                                         \
  49 static const struct gpio_rcar_config                                    \
  50 r8a7791_gpio##idx##_platform_data __initconst = {                       \
  51         .gpio_base      = 32 * (idx),                                   \
  52         .irq_base       = 0,                                            \
  53         .number_of_pins = (nr),                                         \
  54         .pctl_name      = "pfc-r8a7791",                                \
  55         .has_both_edge_trigger = 1,                                     \
  56 };                                                                      \
  57
  58 R8A7791_GPIO(0, 0xe6050000, 32);
  59 R8A7791_GPIO(1, 0xe6051000, 32);
  60 R8A7791_GPIO(2, 0xe6052000, 32);
  61 R8A7791_GPIO(3, 0xe6053000, 32);
  62 R8A7791_GPIO(4, 0xe6054000, 32);
  63 R8A7791_GPIO(5, 0xe6055000, 32);
  64 R8A7791_GPIO(6, 0xe6055400, 32);
  65 R8A7791_GPIO(7, 0xe6055800, 26);
  66
  67 #define r8a7791_register_gpio(idx)                                      \
  68         platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
  69                 r8a7791_gpio##idx##_resources,                          \
  70                 ARRAY_SIZE(r8a7791_gpio##idx##_resources),              \
  71                 &r8a7791_gpio##idx##_platform_data,                     \
  72                 sizeof(r8a7791_gpio##idx##_platform_data))
  73
  74 void __init r8a7791_pinmux_init(void)
  75 {
  76         r8a7791_register_pfc();
  77         r8a7791_register_gpio(0);
  78         r8a7791_register_gpio(1);
  79         r8a7791_register_gpio(2);
  80         r8a7791_register_gpio(3);
  81         r8a7791_register_gpio(4);
  82         r8a7791_register_gpio(5);
  83         r8a7791_register_gpio(6);
  84         r8a7791_register_gpio(7);
  85 }
  86
  87 #define __R8A7791_SCIF(scif_type, index, baseaddr, irq)                 \
  88 static struct plat_sci_port scif##index##_platform_data = {             \
  89         .type           = scif_type,                                    \
  90         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
  91         .scscr          = SCSCR_RE | SCSCR_TE,                          \
  92 };                                                                      \
  93                                                                         \
  94 static struct resource scif##index##_resources[] = {                    \
  95         DEFINE_RES_MEM(baseaddr, 0x100),                                \
  96         DEFINE_RES_IRQ(irq),                                            \
  97 }
  98
  99 #define R8A7791_SCIF(index, baseaddr, irq)                              \
 100         __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq)
 101
 102 #define R8A7791_SCIFA(index, baseaddr, irq)                             \
 103         __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq)
 104
 105 #define R8A7791_SCIFB(index, baseaddr, irq)                             \
 106         __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq)
 107
 108 R8A7791_SCIFA(0,  0xe6c40000, gic_spi(144)); /* SCIFA0 */
 109 R8A7791_SCIFA(1,  0xe6c50000, gic_spi(145)); /* SCIFA1 */
 110 R8A7791_SCIFB(2,  0xe6c20000, gic_spi(148)); /* SCIFB0 */
 111 R8A7791_SCIFB(3,  0xe6c30000, gic_spi(149)); /* SCIFB1 */
 112 R8A7791_SCIFB(4,  0xe6ce0000, gic_spi(150)); /* SCIFB2 */
 113 R8A7791_SCIFA(5,  0xe6c60000, gic_spi(151)); /* SCIFA2 */
 114 R8A7791_SCIF(6,   0xe6e60000, gic_spi(152)); /* SCIF0 */
 115 R8A7791_SCIF(7,   0xe6e68000, gic_spi(153)); /* SCIF1 */
 116 R8A7791_SCIF(8,   0xe6e58000, gic_spi(22)); /* SCIF2 */
 117 R8A7791_SCIF(9,   0xe6ea8000, gic_spi(23)); /* SCIF3 */
 118 R8A7791_SCIF(10,  0xe6ee0000, gic_spi(24)); /* SCIF4 */
 119 R8A7791_SCIF(11,  0xe6ee8000, gic_spi(25)); /* SCIF5 */
 120 R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */
 121 R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */
 122 R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
 123
 124 #define r8a7791_register_scif(index)                                           \
 125         platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
 126                                           scif##index##_resources,             \
 127                                           ARRAY_SIZE(scif##index##_resources), \
 128                                           &scif##index##_platform_data,        \
 129                                           sizeof(scif##index##_platform_data))
 130
 131 static const struct sh_timer_config cmt00_platform_data __initconst = {
 132         .name = "CMT00",
 133         .timer_bit = 0,
 134         .clockevent_rating = 80,
 135 };
 136
 137 static const struct resource cmt00_resources[] __initconst = {
 138         DEFINE_RES_MEM(0xffca0510, 0x0c),
 139         DEFINE_RES_MEM(0xffca0500, 0x04),
 140         DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
 141 };
 142
 143 #define r8a7791_register_cmt(idx)                                       \
 144         platform_device_register_resndata(&platform_bus, "sh_cmt",      \
 145                                           idx, cmt##idx##_resources,    \
 146                                           ARRAY_SIZE(cmt##idx##_resources), \
 147                                           &cmt##idx##_platform_data,    \
 148                                           sizeof(struct sh_timer_config))
 149
 150 static struct renesas_irqc_config irqc0_data = {
 151         .irq_base = irq_pin(0), /* IRQ0 -> IRQ9 */
 152 };
 153
 154 static struct resource irqc0_resources[] = {
 155         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
 156         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
 157         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
 158         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
 159         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
 160         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
 161         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
 162         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
 163         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
 164         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
 165         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
 166 };
 167
 168 #define r8a7791_register_irqc(idx)                                      \
 169         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
 170                                           idx, irqc##idx##_resources,   \
 171                                           ARRAY_SIZE(irqc##idx##_resources), \
 172                                           &irqc##idx##_data,            \
 173                                           sizeof(struct renesas_irqc_config))
 174
 175 static const struct resource thermal_resources[] __initconst = {
 176         DEFINE_RES_MEM(0xe61f0000, 0x14),
 177         DEFINE_RES_MEM(0xe61f0100, 0x38),
 178         DEFINE_RES_IRQ(gic_spi(69)),
 179 };
 180
 181 #define r8a7791_register_thermal()                                      \
 182         platform_device_register_simple("rcar_thermal", -1,             \
 183                                         thermal_resources,              \
 184                                         ARRAY_SIZE(thermal_resources))
 185
 186 void __init r8a7791_add_dt_devices(void)
 187 {
 188         r8a7791_register_scif(0);
 189         r8a7791_register_scif(1);
 190         r8a7791_register_scif(2);
 191         r8a7791_register_scif(3);
 192         r8a7791_register_scif(4);
 193         r8a7791_register_scif(5);
 194         r8a7791_register_scif(6);
 195         r8a7791_register_scif(7);
 196         r8a7791_register_scif(8);
 197         r8a7791_register_scif(9);
 198         r8a7791_register_scif(10);
 199         r8a7791_register_scif(11);
 200         r8a7791_register_scif(12);
 201         r8a7791_register_scif(13);
 202         r8a7791_register_scif(14);
 203         r8a7791_register_cmt(00);
 204 }
 205
 206 void __init r8a7791_add_standard_devices(void)
 207 {
 208         r8a7791_add_dt_devices();
 209         r8a7791_register_irqc(0);
 210         r8a7791_register_thermal();
 211 }
 212
 213 void __init r8a7791_init_early(void)
 214 {
 215 #ifndef CONFIG_ARM_ARCH_TIMER
 216         shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
 217 #endif
 218 }
 219
 220 #ifdef CONFIG_USE_OF
 221 static const char *r8a7791_boards_compat_dt[] __initdata = {
 222         "renesas,r8a7791",
 223         NULL,
 224 };
 225
 226 DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
 227         .smp            = smp_ops(r8a7791_smp_ops),
 228         .init_early     = r8a7791_init_early,
 229         .init_time      = rcar_gen2_timer_init,
 230         .dt_compat      = r8a7791_boards_compat_dt,
 231 MACHINE_END
 232 #endif /* CONFIG_USE_OF */