2 * r8a7790 processor support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/irq.h>
22 #include <linux/kernel.h>
23 #include <linux/of_platform.h>
24 #include <linux/serial_sci.h>
25 #include <linux/platform_data/gpio-rcar.h>
26 #include <linux/platform_data/irq-renesas-irqc.h>
27 #include <mach/common.h>
28 #include <mach/irqs.h>
29 #include <mach/r8a7790.h>
30 #include <asm/mach/arch.h>
32 static struct resource pfc_resources[] __initdata = {
33 DEFINE_RES_MEM(0xe6060000, 0x250),
36 #define R8A7790_GPIO(idx) \
37 static struct resource r8a7790_gpio##idx##_resources[] __initdata = { \
38 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
39 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
42 static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
43 .gpio_base = 32 * (idx), \
45 .number_of_pins = 32, \
46 .pctl_name = "pfc-r8a7790", \
47 .has_both_edge_trigger = 1, \
57 #define r8a7790_register_gpio(idx) \
58 platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
59 r8a7790_gpio##idx##_resources, \
60 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
61 &r8a7790_gpio##idx##_platform_data, \
62 sizeof(r8a7790_gpio##idx##_platform_data))
64 void __init r8a7790_pinmux_init(void)
66 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
67 ARRAY_SIZE(pfc_resources));
68 r8a7790_register_gpio(0);
69 r8a7790_register_gpio(1);
70 r8a7790_register_gpio(2);
71 r8a7790_register_gpio(3);
72 r8a7790_register_gpio(4);
73 r8a7790_register_gpio(5);
76 #define SCIF_COMMON(scif_type, baseaddr, irq) \
78 .mapbase = baseaddr, \
79 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
80 .irqs = SCIx_IRQ_MUXED(irq)
82 #define SCIFA_DATA(index, baseaddr, irq) \
84 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
85 .scbrr_algo_id = SCBRR_ALGO_4, \
86 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
89 #define SCIFB_DATA(index, baseaddr, irq) \
91 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
92 .scbrr_algo_id = SCBRR_ALGO_4, \
93 .scscr = SCSCR_RE | SCSCR_TE, \
96 #define SCIF_DATA(index, baseaddr, irq) \
98 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
99 .scbrr_algo_id = SCBRR_ALGO_2, \
100 .scscr = SCSCR_RE | SCSCR_TE, \
103 #define HSCIF_DATA(index, baseaddr, irq) \
105 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
106 .scbrr_algo_id = SCBRR_ALGO_6, \
107 .scscr = SCSCR_RE | SCSCR_TE, \
110 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
113 static struct plat_sci_port scif[] __initdata = {
114 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
115 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
116 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
117 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
118 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
119 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
120 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
121 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
122 HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
123 HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
126 static inline void r8a7790_register_scif(int idx)
128 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
129 sizeof(struct plat_sci_port));
132 static struct renesas_irqc_config irqc0_data __initdata = {
133 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
136 static struct resource irqc0_resources[] __initdata = {
137 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
138 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
139 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
140 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
141 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
144 #define r8a7790_register_irqc(idx) \
145 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
146 idx, irqc##idx##_resources, \
147 ARRAY_SIZE(irqc##idx##_resources), \
149 sizeof(struct renesas_irqc_config))
151 void __init r8a7790_add_standard_devices(void)
153 r8a7790_register_scif(SCIFA0);
154 r8a7790_register_scif(SCIFA1);
155 r8a7790_register_scif(SCIFB0);
156 r8a7790_register_scif(SCIFB1);
157 r8a7790_register_scif(SCIFB2);
158 r8a7790_register_scif(SCIFA2);
159 r8a7790_register_scif(SCIF0);
160 r8a7790_register_scif(SCIF1);
161 r8a7790_register_scif(HSCIF0);
162 r8a7790_register_scif(HSCIF1);
163 r8a7790_register_irqc(0);
166 void __init r8a7790_timer_init(void)
170 /* make sure arch timer is started by setting bit 0 of CNTCT */
171 cntcr = ioremap(0xe6080000, PAGE_SIZE);
175 shmobile_timer_init();
179 void __init r8a7790_add_standard_devices_dt(void)
181 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
184 static const char *r8a7790_boards_compat_dt[] __initdata = {
189 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
190 .init_machine = r8a7790_add_standard_devices_dt,
191 .init_time = r8a7790_timer_init,
192 .dt_compat = r8a7790_boards_compat_dt,
194 #endif /* CONFIG_USE_OF */