arch/arm/mach-shmobile/setup-r8a7778.c

   1 /*
   2  * r8a7778 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/io.h>
  20 #include <linux/irqchip/arm-gic.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_data/dma-rcar-hpbdma.h>
  24 #include <linux/platform_data/gpio-rcar.h>
  25 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/irqchip.h>
  28 #include <linux/serial_sci.h>
  29 #include <linux/sh_timer.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/usb/phy.h>
  32 #include <linux/usb/hcd.h>
  33 #include <linux/usb/ehci_pdriver.h>
  34 #include <linux/usb/ohci_pdriver.h>
  35 #include <linux/dma-mapping.h>
  36
  37 #include <asm/mach/arch.h>
  38 #include <asm/hardware/cache-l2x0.h>
  39
  40 #include "common.h"
  41 #include "irqs.h"
  42 #include "r8a7778.h"
  43
  44 /* SCIF */
  45 #define R8A7778_SCIF(index, baseaddr, irq)                      \
  46 static struct plat_sci_port scif##index##_platform_data = {     \
  47         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  48         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
  49         .type           = PORT_SCIF,                            \
  50 };                                                              \
  51                                                                 \
  52 static struct resource scif##index##_resources[] = {            \
  53         DEFINE_RES_MEM(baseaddr, 0x100),                        \
  54         DEFINE_RES_IRQ(irq),                                    \
  55 }
  56
  57 R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
  58 R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
  59 R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
  60 R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
  61 R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
  62 R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
  63
  64 #define r8a7778_register_scif(index)                                           \
  65         platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
  66                                           scif##index##_resources,             \
  67                                           ARRAY_SIZE(scif##index##_resources), \
  68                                           &scif##index##_platform_data,        \
  69                                           sizeof(scif##index##_platform_data))
  70
  71 /* TMU */
  72 static struct sh_timer_config sh_tmu0_platform_data = {
  73         .channels_mask = 7,
  74 };
  75
  76 static struct resource sh_tmu0_resources[] = {
  77         DEFINE_RES_MEM(0xffd80000, 0x30),
  78         DEFINE_RES_IRQ(gic_iid(0x40)),
  79         DEFINE_RES_IRQ(gic_iid(0x41)),
  80         DEFINE_RES_IRQ(gic_iid(0x42)),
  81 };
  82
  83 #define r8a7778_register_tmu(idx)                       \
  84         platform_device_register_resndata(              \
  85                 &platform_bus, "sh-tmu", idx,           \
  86                 sh_tmu##idx##_resources,                \
  87                 ARRAY_SIZE(sh_tmu##idx##_resources),    \
  88                 &sh_tmu##idx##_platform_data,           \
  89                 sizeof(sh_tmu##idx##_platform_data))
  90
  91 int r8a7778_usb_phy_power(bool enable)
  92 {
  93         static struct usb_phy *phy = NULL;
  94         int ret = 0;
  95
  96         if (!phy)
  97                 phy = usb_get_phy(USB_PHY_TYPE_USB2);
  98
  99         if (IS_ERR(phy)) {
 100                 pr_err("kernel doesn't have usb phy driver\n");
 101                 return PTR_ERR(phy);
 102         }
 103
 104         if (enable)
 105                 ret = usb_phy_init(phy);
 106         else
 107                 usb_phy_shutdown(phy);
 108
 109         return ret;
 110 }
 111
 112 /* USB */
 113 static int usb_power_on(struct platform_device *pdev)
 114 {
 115         int ret = r8a7778_usb_phy_power(true);
 116
 117         if (ret)
 118                 return ret;
 119
 120         pm_runtime_enable(&pdev->dev);
 121         pm_runtime_get_sync(&pdev->dev);
 122
 123         return 0;
 124 }
 125
 126 static void usb_power_off(struct platform_device *pdev)
 127 {
 128         if (r8a7778_usb_phy_power(false))
 129                 return;
 130
 131         pm_runtime_put_sync(&pdev->dev);
 132         pm_runtime_disable(&pdev->dev);
 133 }
 134
 135 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
 136 {
 137         /*
 138          * Below are recommended values from the datasheet;
 139          * see [USB :: Setting of EHCI Internal Buffer].
 140          */
 141         /* EHCI IP internal buffer setting */
 142         iowrite32(0x00ff0040, hcd->regs + 0x0094);
 143         /* EHCI IP internal buffer enable */
 144         iowrite32(0x00000001, hcd->regs + 0x009C);
 145
 146         return 0;
 147 }
 148
 149 static struct usb_ehci_pdata ehci_pdata __initdata = {
 150         .power_on       = usb_power_on,
 151         .power_off      = usb_power_off,
 152         .power_suspend  = usb_power_off,
 153         .pre_setup      = ehci_init_internal_buffer,
 154 };
 155
 156 static struct resource ehci_resources[] __initdata = {
 157         DEFINE_RES_MEM(0xffe70000, 0x400),
 158         DEFINE_RES_IRQ(gic_iid(0x4c)),
 159 };
 160
 161 static struct usb_ohci_pdata ohci_pdata __initdata = {
 162         .power_on       = usb_power_on,
 163         .power_off      = usb_power_off,
 164         .power_suspend  = usb_power_off,
 165 };
 166
 167 static struct resource ohci_resources[] __initdata = {
 168         DEFINE_RES_MEM(0xffe70400, 0x400),
 169         DEFINE_RES_IRQ(gic_iid(0x4c)),
 170 };
 171
 172 #define USB_PLATFORM_INFO(hci)                                  \
 173 static struct platform_device_info hci##_info __initdata = {    \
 174         .parent         = &platform_bus,                        \
 175         .name           = #hci "-platform",                     \
 176         .id             = -1,                                   \
 177         .res            = hci##_resources,                      \
 178         .num_res        = ARRAY_SIZE(hci##_resources),          \
 179         .data           = &hci##_pdata,                         \
 180         .size_data      = sizeof(hci##_pdata),                  \
 181         .dma_mask       = DMA_BIT_MASK(32),                     \
 182 }
 183
 184 USB_PLATFORM_INFO(ehci);
 185 USB_PLATFORM_INFO(ohci);
 186
 187 /* PFC/GPIO */
 188 static struct resource pfc_resources[] __initdata = {
 189         DEFINE_RES_MEM(0xfffc0000, 0x118),
 190 };
 191
 192 #define R8A7778_GPIO(idx)                                               \
 193 static struct resource r8a7778_gpio##idx##_resources[] __initdata = {   \
 194         DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
 195         DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
 196 };                                                                      \
 197                                                                         \
 198 static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
 199         .gpio_base      = 32 * (idx),                                   \
 200         .irq_base       = GPIO_IRQ_BASE(idx),                           \
 201         .number_of_pins = 32,                                           \
 202         .pctl_name      = "pfc-r8a7778",                                \
 203 }
 204
 205 R8A7778_GPIO(0);
 206 R8A7778_GPIO(1);
 207 R8A7778_GPIO(2);
 208 R8A7778_GPIO(3);
 209 R8A7778_GPIO(4);
 210
 211 #define r8a7778_register_gpio(idx)                              \
 212         platform_device_register_resndata(                      \
 213                 &platform_bus, "gpio_rcar", idx,                \
 214                 r8a7778_gpio##idx##_resources,                  \
 215                 ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
 216                 &r8a7778_gpio##idx##_platform_data,             \
 217                 sizeof(r8a7778_gpio##idx##_platform_data))
 218
 219 void __init r8a7778_pinmux_init(void)
 220 {
 221         platform_device_register_simple(
 222                 "pfc-r8a7778", -1,
 223                 pfc_resources,
 224                 ARRAY_SIZE(pfc_resources));
 225
 226         r8a7778_register_gpio(0);
 227         r8a7778_register_gpio(1);
 228         r8a7778_register_gpio(2);
 229         r8a7778_register_gpio(3);
 230         r8a7778_register_gpio(4);
 231 };
 232
 233 /* I2C */
 234 static struct resource i2c_resources[] __initdata = {
 235         /* I2C0 */
 236         DEFINE_RES_MEM(0xffc70000, 0x1000),
 237         DEFINE_RES_IRQ(gic_iid(0x63)),
 238         /* I2C1 */
 239         DEFINE_RES_MEM(0xffc71000, 0x1000),
 240         DEFINE_RES_IRQ(gic_iid(0x6e)),
 241         /* I2C2 */
 242         DEFINE_RES_MEM(0xffc72000, 0x1000),
 243         DEFINE_RES_IRQ(gic_iid(0x6c)),
 244         /* I2C3 */
 245         DEFINE_RES_MEM(0xffc73000, 0x1000),
 246         DEFINE_RES_IRQ(gic_iid(0x6d)),
 247 };
 248
 249 static void __init r8a7778_register_i2c(int id)
 250 {
 251         BUG_ON(id < 0 || id > 3);
 252
 253         platform_device_register_simple(
 254                 "i2c-rcar", id,
 255                 i2c_resources + (2 * id), 2);
 256 }
 257
 258 /* HSPI */
 259 static struct resource hspi_resources[] __initdata = {
 260         /* HSPI0 */
 261         DEFINE_RES_MEM(0xfffc7000, 0x18),
 262         DEFINE_RES_IRQ(gic_iid(0x5f)),
 263         /* HSPI1 */
 264         DEFINE_RES_MEM(0xfffc8000, 0x18),
 265         DEFINE_RES_IRQ(gic_iid(0x74)),
 266         /* HSPI2 */
 267         DEFINE_RES_MEM(0xfffc6000, 0x18),
 268         DEFINE_RES_IRQ(gic_iid(0x75)),
 269 };
 270
 271 static void __init r8a7778_register_hspi(int id)
 272 {
 273         BUG_ON(id < 0 || id > 2);
 274
 275         platform_device_register_simple(
 276                 "sh-hspi", id,
 277                 hspi_resources + (2 * id), 2);
 278 }
 279
 280 void __init r8a7778_add_dt_devices(void)
 281 {
 282 #ifdef CONFIG_CACHE_L2X0
 283         void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
 284         if (base) {
 285                 /*
 286                  * Early BRESP enable, Shared attribute override enable, 64K*16way
 287                  * don't call iounmap(base)
 288                  */
 289                 l2x0_init(base, 0x40470000, 0x82000fff);
 290         }
 291 #endif
 292 }
 293
 294 /* HPB-DMA */
 295
 296 /* Asynchronous mode register (ASYNCMDR) bits */
 297 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK   BIT(2)  /* SDHI0 */
 298 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2)  /* SDHI0 */
 299 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI  0       /* SDHI0 */
 300 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK   BIT(1)  /* SDHI0 */
 301 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)  /* SDHI0 */
 302 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI  0       /* SDHI0 */
 303
 304 #define HPBDMA_SSI(_id)                         \
 305 {                                               \
 306         .id     = HPBDMA_SLAVE_SSI## _id ##_TX, \
 307         .addr   = 0xffd91008 + (_id * 0x40),    \
 308         .dcr    = HPB_DMAE_DCR_CT |             \
 309                   HPB_DMAE_DCR_DIP |            \
 310                   HPB_DMAE_DCR_SPDS_32BIT |     \
 311                   HPB_DMAE_DCR_DMDL |           \
 312                   HPB_DMAE_DCR_DPDS_32BIT,      \
 313         .port   = _id + (_id << 8),             \
 314         .dma_ch = (28 + _id),                   \
 315 }, {                                            \
 316         .id     = HPBDMA_SLAVE_SSI## _id ##_RX, \
 317         .addr   = 0xffd9100c + (_id * 0x40),    \
 318         .dcr    = HPB_DMAE_DCR_CT |             \
 319                   HPB_DMAE_DCR_DIP |            \
 320                   HPB_DMAE_DCR_SMDL |           \
 321                   HPB_DMAE_DCR_SPDS_32BIT |     \
 322                   HPB_DMAE_DCR_DPDS_32BIT,      \
 323         .port   = _id + (_id << 8),             \
 324         .dma_ch = (28 + _id),                   \
 325 }
 326
 327 #define HPBDMA_HPBIF(_id)                               \
 328 {                                                       \
 329         .id     = HPBDMA_SLAVE_HPBIF## _id ##_TX,       \
 330         .addr   = 0xffda0000 + (_id * 0x1000),          \
 331         .dcr    = HPB_DMAE_DCR_CT |                     \
 332                   HPB_DMAE_DCR_DIP |                    \
 333                   HPB_DMAE_DCR_SPDS_32BIT |             \
 334                   HPB_DMAE_DCR_DMDL |                   \
 335                   HPB_DMAE_DCR_DPDS_32BIT,              \
 336         .port   = 0x1111,                               \
 337         .dma_ch = (28 + _id),                           \
 338 }, {                                                    \
 339         .id     = HPBDMA_SLAVE_HPBIF## _id ##_RX,       \
 340         .addr   = 0xffda0000 + (_id * 0x1000),          \
 341         .dcr    = HPB_DMAE_DCR_CT |                     \
 342                   HPB_DMAE_DCR_DIP |                    \
 343                   HPB_DMAE_DCR_SMDL |                   \
 344                   HPB_DMAE_DCR_SPDS_32BIT |             \
 345                   HPB_DMAE_DCR_DPDS_32BIT,              \
 346         .port   = 0x1111,                               \
 347         .dma_ch = (28 + _id),                           \
 348 }
 349
 350 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
 351         {
 352                 .id     = HPBDMA_SLAVE_SDHI0_TX,
 353                 .addr   = 0xffe4c000 + 0x30,
 354                 .dcr    = HPB_DMAE_DCR_SPDS_16BIT |
 355                           HPB_DMAE_DCR_DMDL |
 356                           HPB_DMAE_DCR_DPDS_16BIT,
 357                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 358                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 359                           HPB_DMAE_ASYNCRSTR_ASRST23,
 360                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
 361                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
 362                 .port   = 0x0D0C,
 363                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 364                 .dma_ch = 21,
 365         }, {
 366                 .id     = HPBDMA_SLAVE_SDHI0_RX,
 367                 .addr   = 0xffe4c000 + 0x30,
 368                 .dcr    = HPB_DMAE_DCR_SMDL |
 369                           HPB_DMAE_DCR_SPDS_16BIT |
 370                           HPB_DMAE_DCR_DPDS_16BIT,
 371                 .rstr   = HPB_DMAE_ASYNCRSTR_ASRST21 |
 372                           HPB_DMAE_ASYNCRSTR_ASRST22 |
 373                           HPB_DMAE_ASYNCRSTR_ASRST23,
 374                 .mdr    = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
 375                 .mdm    = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
 376                 .port   = 0x0D0C,
 377                 .flags  = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
 378                 .dma_ch = 22,
 379         }, {
 380                 .id     = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
 381                 .addr   = 0xffe60018,
 382                 .dcr    = HPB_DMAE_DCR_SPDS_32BIT |
 383                           HPB_DMAE_DCR_DMDL |
 384                           HPB_DMAE_DCR_DPDS_32BIT,
 385                 .port   = 0x0000,
 386                 .dma_ch = 14,
 387         }, {
 388                 .id     = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
 389                 .addr   = 0xffe6001c,
 390                 .dcr    = HPB_DMAE_DCR_SMDL |
 391                           HPB_DMAE_DCR_SPDS_32BIT |
 392                           HPB_DMAE_DCR_DPDS_32BIT,
 393                 .port   = 0x0101,
 394                 .dma_ch = 15,
 395         },
 396
 397         HPBDMA_SSI(0),
 398         HPBDMA_SSI(1),
 399         HPBDMA_SSI(2),
 400         HPBDMA_SSI(3),
 401         HPBDMA_SSI(4),
 402         HPBDMA_SSI(5),
 403         HPBDMA_SSI(6),
 404         HPBDMA_SSI(7),
 405         HPBDMA_SSI(8),
 406
 407         HPBDMA_HPBIF(0),
 408         HPBDMA_HPBIF(1),
 409         HPBDMA_HPBIF(2),
 410         HPBDMA_HPBIF(3),
 411         HPBDMA_HPBIF(4),
 412         HPBDMA_HPBIF(5),
 413         HPBDMA_HPBIF(6),
 414         HPBDMA_HPBIF(7),
 415         HPBDMA_HPBIF(8),
 416 };
 417
 418 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
 419         HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
 420         HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
 421         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
 422         HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
 423         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
 424         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
 425         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
 426         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
 427         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
 428         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
 429         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
 430         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
 431         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
 432         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
 433         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
 434         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
 435         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
 436         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
 437         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
 438         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
 439         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
 440         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
 441         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
 442         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
 443         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
 444         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
 445         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
 446         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
 447         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
 448         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
 449         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
 450         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
 451         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
 452         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
 453         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
 454         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
 455         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
 456         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
 457         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
 458         HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
 459 };
 460
 461 static struct hpb_dmae_pdata dma_platform_data __initdata = {
 462         .slaves                 = hpb_dmae_slaves,
 463         .num_slaves             = ARRAY_SIZE(hpb_dmae_slaves),
 464         .channels               = hpb_dmae_channels,
 465         .num_channels           = ARRAY_SIZE(hpb_dmae_channels),
 466         .ts_shift               = {
 467                 [XMIT_SZ_8BIT]  = 0,
 468                 [XMIT_SZ_16BIT] = 1,
 469                 [XMIT_SZ_32BIT] = 2,
 470         },
 471         .num_hw_channels        = 39,
 472 };
 473
 474 static struct resource hpb_dmae_resources[] __initdata = {
 475         /* Channel registers */
 476         DEFINE_RES_MEM(0xffc08000, 0x1000),
 477         /* Common registers */
 478         DEFINE_RES_MEM(0xffc09000, 0x170),
 479         /* Asynchronous reset registers */
 480         DEFINE_RES_MEM(0xffc00300, 4),
 481         /* Asynchronous mode registers */
 482         DEFINE_RES_MEM(0xffc00400, 4),
 483         /* IRQ for DMA channels */
 484         DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
 485 };
 486
 487 static void __init r8a7778_register_hpb_dmae(void)
 488 {
 489         platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
 490                                           hpb_dmae_resources,
 491                                           ARRAY_SIZE(hpb_dmae_resources),
 492                                           &dma_platform_data,
 493                                           sizeof(dma_platform_data));
 494 }
 495
 496 void __init r8a7778_add_standard_devices(void)
 497 {
 498         r8a7778_add_dt_devices();
 499         r8a7778_register_tmu(0);
 500         r8a7778_register_scif(0);
 501         r8a7778_register_scif(1);
 502         r8a7778_register_scif(2);
 503         r8a7778_register_scif(3);
 504         r8a7778_register_scif(4);
 505         r8a7778_register_scif(5);
 506         r8a7778_register_i2c(0);
 507         r8a7778_register_i2c(1);
 508         r8a7778_register_i2c(2);
 509         r8a7778_register_i2c(3);
 510         r8a7778_register_hspi(0);
 511         r8a7778_register_hspi(1);
 512         r8a7778_register_hspi(2);
 513
 514         r8a7778_register_hpb_dmae();
 515 }
 516
 517 void __init r8a7778_init_late(void)
 518 {
 519         shmobile_init_late();
 520         platform_device_register_full(&ehci_info);
 521         platform_device_register_full(&ohci_info);
 522 }
 523
 524 static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
 525         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 526         .sense_bitfield_width = 2,
 527 };
 528
 529 static struct resource irqpin_resources[] __initdata = {
 530         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
 531         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
 532         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
 533         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
 534         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
 535         DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
 536         DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
 537         DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
 538         DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
 539 };
 540
 541 void __init r8a7778_init_irq_extpin_dt(int irlm)
 542 {
 543         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 544         unsigned long tmp;
 545
 546         if (!icr0) {
 547                 pr_warn("r8a7778: unable to setup external irq pin mode\n");
 548                 return;
 549         }
 550
 551         tmp = ioread32(icr0);
 552         if (irlm)
 553                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 554         else
 555                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 556         tmp |= (1 << 21); /* LVLMODE = 1 */
 557         iowrite32(tmp, icr0);
 558         iounmap(icr0);
 559 }
 560
 561 void __init r8a7778_init_irq_extpin(int irlm)
 562 {
 563         r8a7778_init_irq_extpin_dt(irlm);
 564         if (irlm)
 565                 platform_device_register_resndata(
 566                         &platform_bus, "renesas_intc_irqpin", -1,
 567                         irqpin_resources, ARRAY_SIZE(irqpin_resources),
 568                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 569 }
 570
 571 #ifdef CONFIG_USE_OF
 572 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 573 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 574
 575 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 576 #define INT2NTSR1       0x0002c /* 0xfe70002c */
 577 void __init r8a7778_init_irq_dt(void)
 578 {
 579         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 580
 581         BUG_ON(!base);
 582
 583         irqchip_init();
 584
 585         /* route all interrupts to ARM */
 586         __raw_writel(0x73ffffff, base + INT2NTSR0);
 587         __raw_writel(0xffffffff, base + INT2NTSR1);
 588
 589         /* unmask all known interrupts in INTCS2 */
 590         __raw_writel(0x08330773, base + INT2SMSKCR0);
 591         __raw_writel(0x00311110, base + INT2SMSKCR1);
 592
 593         iounmap(base);
 594 }
 595
 596 static const char *r8a7778_compat_dt[] __initdata = {
 597         "renesas,r8a7778",
 598         NULL,
 599 };
 600
 601 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
 602         .init_early     = shmobile_init_delay,
 603         .init_irq       = r8a7778_init_irq_dt,
 604         .init_late      = shmobile_init_late,
 605         .dt_compat      = r8a7778_compat_dt,
 606 MACHINE_END
 607
 608 #endif /* CONFIG_USE_OF */