arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34 #include <mach/dma-register.h>
  35 #include <mach/r8a7740.h>
  36 #include <mach/pm-rmobile.h>
  37 #include <mach/common.h>
  38 #include <mach/irqs.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43
  44 static struct map_desc r8a7740_io_desc[] __initdata = {
  45          /*
  46           * for CPGA/INTC/PFC
  47           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  48           */
  49         {
  50                 .virtual        = 0xe6000000,
  51                 .pfn            = __phys_to_pfn(0xe6000000),
  52                 .length         = 160 << 20,
  53                 .type           = MT_DEVICE_NONSHARED
  54         },
  55 #ifdef CONFIG_CACHE_L2X0
  56         /*
  57          * for l2x0_init()
  58          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  59          */
  60         {
  61                 .virtual        = 0xf0002000,
  62                 .pfn            = __phys_to_pfn(0xf0100000),
  63                 .length         = PAGE_SIZE,
  64                 .type           = MT_DEVICE_NONSHARED
  65         },
  66 #endif
  67 };
  68
  69 void __init r8a7740_map_io(void)
  70 {
  71         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  72 }
  73
  74 /* PFC */
  75 static const struct resource pfc_resources[] = {
  76         DEFINE_RES_MEM(0xe6050000, 0x8000),
  77         DEFINE_RES_MEM(0xe605800c, 0x0020),
  78 };
  79
  80 void __init r8a7740_pinmux_init(void)
  81 {
  82         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  83                                         ARRAY_SIZE(pfc_resources));
  84 }
  85
  86 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  87         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  88 };
  89
  90 static struct resource irqpin0_resources[] = {
  91         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  92         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  93         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  94         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  95         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  96         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
  97         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
  98         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 103         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 104 };
 105
 106 static struct platform_device irqpin0_device = {
 107         .name           = "renesas_intc_irqpin",
 108         .id             = 0,
 109         .resource       = irqpin0_resources,
 110         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 111         .dev            = {
 112                 .platform_data  = &irqpin0_platform_data,
 113         },
 114 };
 115
 116 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 117         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 118 };
 119
 120 static struct resource irqpin1_resources[] = {
 121         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 122         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 123         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 124         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 125         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 126         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 127         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 128         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 133         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 134 };
 135
 136 static struct platform_device irqpin1_device = {
 137         .name           = "renesas_intc_irqpin",
 138         .id             = 1,
 139         .resource       = irqpin1_resources,
 140         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 141         .dev            = {
 142                 .platform_data  = &irqpin1_platform_data,
 143         },
 144 };
 145
 146 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 147         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 148 };
 149
 150 static struct resource irqpin2_resources[] = {
 151         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 152         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 153         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 154         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 155         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 156         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 157         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 158         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 163         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 164 };
 165
 166 static struct platform_device irqpin2_device = {
 167         .name           = "renesas_intc_irqpin",
 168         .id             = 2,
 169         .resource       = irqpin2_resources,
 170         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 171         .dev            = {
 172                 .platform_data  = &irqpin2_platform_data,
 173         },
 174 };
 175
 176 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 177         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 178 };
 179
 180 static struct resource irqpin3_resources[] = {
 181         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 182         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 183         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 184         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 185         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 186         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 187         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 188         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 193         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 194 };
 195
 196 static struct platform_device irqpin3_device = {
 197         .name           = "renesas_intc_irqpin",
 198         .id             = 3,
 199         .resource       = irqpin3_resources,
 200         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 201         .dev            = {
 202                 .platform_data  = &irqpin3_platform_data,
 203         },
 204 };
 205
 206 /* SCIF */
 207 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 208 static struct plat_sci_port scif##index##_platform_data = {     \
 209         .type           = scif_type,                            \
 210         .mapbase        = baseaddr,                             \
 211         .flags          = UPF_BOOT_AUTOCONF,                    \
 212         .irqs           = SCIx_IRQ_MUXED(irq),                  \
 213         .scbrr_algo_id  = SCBRR_ALGO_4,                         \
 214         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 215 };                                                              \
 216                                                                 \
 217 static struct platform_device scif##index##_device = {          \
 218         .name           = "sh-sci",                             \
 219         .id             = index,                                \
 220         .dev            = {                                     \
 221                 .platform_data  = &scif##index##_platform_data, \
 222         },                                                      \
 223 }
 224
 225 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 226 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 227 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 228 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 229 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 230 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 231 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 232 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 233 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 234
 235 /* CMT */
 236 static struct sh_timer_config cmt10_platform_data = {
 237         .name = "CMT10",
 238         .channel_offset = 0x10,
 239         .timer_bit = 0,
 240         .clockevent_rating = 125,
 241         .clocksource_rating = 125,
 242 };
 243
 244 static struct resource cmt10_resources[] = {
 245         [0] = {
 246                 .name   = "CMT10",
 247                 .start  = 0xe6138010,
 248                 .end    = 0xe613801b,
 249                 .flags  = IORESOURCE_MEM,
 250         },
 251         [1] = {
 252                 .start  = gic_spi(58),
 253                 .flags  = IORESOURCE_IRQ,
 254         },
 255 };
 256
 257 static struct platform_device cmt10_device = {
 258         .name           = "sh_cmt",
 259         .id             = 10,
 260         .dev = {
 261                 .platform_data  = &cmt10_platform_data,
 262         },
 263         .resource       = cmt10_resources,
 264         .num_resources  = ARRAY_SIZE(cmt10_resources),
 265 };
 266
 267 /* TMU */
 268 static struct sh_timer_config tmu00_platform_data = {
 269         .name = "TMU00",
 270         .channel_offset = 0x4,
 271         .timer_bit = 0,
 272         .clockevent_rating = 200,
 273 };
 274
 275 static struct resource tmu00_resources[] = {
 276         [0] = {
 277                 .name   = "TMU00",
 278                 .start  = 0xfff80008,
 279                 .end    = 0xfff80014 - 1,
 280                 .flags  = IORESOURCE_MEM,
 281         },
 282         [1] = {
 283                 .start  = gic_spi(198),
 284                 .flags  = IORESOURCE_IRQ,
 285         },
 286 };
 287
 288 static struct platform_device tmu00_device = {
 289         .name           = "sh_tmu",
 290         .id             = 0,
 291         .dev = {
 292                 .platform_data  = &tmu00_platform_data,
 293         },
 294         .resource       = tmu00_resources,
 295         .num_resources  = ARRAY_SIZE(tmu00_resources),
 296 };
 297
 298 static struct sh_timer_config tmu01_platform_data = {
 299         .name = "TMU01",
 300         .channel_offset = 0x10,
 301         .timer_bit = 1,
 302         .clocksource_rating = 200,
 303 };
 304
 305 static struct resource tmu01_resources[] = {
 306         [0] = {
 307                 .name   = "TMU01",
 308                 .start  = 0xfff80014,
 309                 .end    = 0xfff80020 - 1,
 310                 .flags  = IORESOURCE_MEM,
 311         },
 312         [1] = {
 313                 .start  = gic_spi(199),
 314                 .flags  = IORESOURCE_IRQ,
 315         },
 316 };
 317
 318 static struct platform_device tmu01_device = {
 319         .name           = "sh_tmu",
 320         .id             = 1,
 321         .dev = {
 322                 .platform_data  = &tmu01_platform_data,
 323         },
 324         .resource       = tmu01_resources,
 325         .num_resources  = ARRAY_SIZE(tmu01_resources),
 326 };
 327
 328 static struct sh_timer_config tmu02_platform_data = {
 329         .name = "TMU02",
 330         .channel_offset = 0x1C,
 331         .timer_bit = 2,
 332         .clocksource_rating = 200,
 333 };
 334
 335 static struct resource tmu02_resources[] = {
 336         [0] = {
 337                 .name   = "TMU02",
 338                 .start  = 0xfff80020,
 339                 .end    = 0xfff8002C - 1,
 340                 .flags  = IORESOURCE_MEM,
 341         },
 342         [1] = {
 343                 .start  = gic_spi(200),
 344                 .flags  = IORESOURCE_IRQ,
 345         },
 346 };
 347
 348 static struct platform_device tmu02_device = {
 349         .name           = "sh_tmu",
 350         .id             = 2,
 351         .dev = {
 352                 .platform_data  = &tmu02_platform_data,
 353         },
 354         .resource       = tmu02_resources,
 355         .num_resources  = ARRAY_SIZE(tmu02_resources),
 356 };
 357
 358 /* IPMMUI (an IPMMU module for ICB/LMB) */
 359 static struct resource ipmmu_resources[] = {
 360         [0] = {
 361                 .name   = "IPMMUI",
 362                 .start  = 0xfe951000,
 363                 .end    = 0xfe9510ff,
 364                 .flags  = IORESOURCE_MEM,
 365         },
 366 };
 367
 368 static const char * const ipmmu_dev_names[] = {
 369         "sh_mobile_lcdc_fb.0",
 370         "sh_mobile_lcdc_fb.1",
 371         "sh_mobile_ceu.0",
 372 };
 373
 374 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 375         .dev_names = ipmmu_dev_names,
 376         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 377 };
 378
 379 static struct platform_device ipmmu_device = {
 380         .name           = "ipmmu",
 381         .id             = -1,
 382         .dev = {
 383                 .platform_data = &ipmmu_platform_data,
 384         },
 385         .resource       = ipmmu_resources,
 386         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 387 };
 388
 389 static struct platform_device *r8a7740_devices_dt[] __initdata = {
 390         &scif0_device,
 391         &scif1_device,
 392         &scif2_device,
 393         &scif3_device,
 394         &scif4_device,
 395         &scif5_device,
 396         &scif6_device,
 397         &scif7_device,
 398         &scif8_device,
 399         &cmt10_device,
 400 };
 401
 402 static struct platform_device *r8a7740_early_devices[] __initdata = {
 403         &irqpin0_device,
 404         &irqpin1_device,
 405         &irqpin2_device,
 406         &irqpin3_device,
 407         &tmu00_device,
 408         &tmu01_device,
 409         &tmu02_device,
 410         &ipmmu_device,
 411 };
 412
 413 /* DMA */
 414 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 415         {
 416                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 417                 .addr           = 0xe6850030,
 418                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 419                 .mid_rid        = 0xc1,
 420         }, {
 421                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 422                 .addr           = 0xe6850030,
 423                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 424                 .mid_rid        = 0xc2,
 425         }, {
 426                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 427                 .addr           = 0xe6860030,
 428                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 429                 .mid_rid        = 0xc9,
 430         }, {
 431                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 432                 .addr           = 0xe6860030,
 433                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 434                 .mid_rid        = 0xca,
 435         }, {
 436                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 437                 .addr           = 0xe6870030,
 438                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 439                 .mid_rid        = 0xcd,
 440         }, {
 441                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 442                 .addr           = 0xe6870030,
 443                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 444                 .mid_rid        = 0xce,
 445         }, {
 446                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 447                 .addr           = 0xfe1f0024,
 448                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 449                 .mid_rid        = 0xb1,
 450         }, {
 451                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 452                 .addr           = 0xfe1f0020,
 453                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 454                 .mid_rid        = 0xb2,
 455         }, {
 456                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 457                 .addr           = 0xfe1f0064,
 458                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 459                 .mid_rid        = 0xb5,
 460         }, {
 461                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 462                 .addr           = 0xe6bd0034,
 463                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 464                 .mid_rid        = 0xd1,
 465         }, {
 466                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 467                 .addr           = 0xe6bd0034,
 468                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 469                 .mid_rid        = 0xd2,
 470         },
 471 };
 472
 473 #define DMA_CHANNEL(a, b, c)                    \
 474 {                                               \
 475         .offset         = a,                    \
 476         .dmars          = b,                    \
 477         .dmars_bit      = c,                    \
 478         .chclr_offset   = (0x220 - 0x20) + a    \
 479 }
 480
 481 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 482         DMA_CHANNEL(0x00, 0, 0),
 483         DMA_CHANNEL(0x10, 0, 8),
 484         DMA_CHANNEL(0x20, 4, 0),
 485         DMA_CHANNEL(0x30, 4, 8),
 486         DMA_CHANNEL(0x50, 8, 0),
 487         DMA_CHANNEL(0x60, 8, 8),
 488 };
 489
 490 static struct sh_dmae_pdata dma_platform_data = {
 491         .slave          = r8a7740_dmae_slaves,
 492         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 493         .channel        = r8a7740_dmae_channels,
 494         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 495         .ts_low_shift   = TS_LOW_SHIFT,
 496         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 497         .ts_high_shift  = TS_HI_SHIFT,
 498         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 499         .ts_shift       = dma_ts_shift,
 500         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 501         .dmaor_init     = DMAOR_DME,
 502         .chclr_present  = 1,
 503 };
 504
 505 /* Resource order important! */
 506 static struct resource r8a7740_dmae0_resources[] = {
 507         {
 508                 /* Channel registers and DMAOR */
 509                 .start  = 0xfe008020,
 510                 .end    = 0xfe00828f,
 511                 .flags  = IORESOURCE_MEM,
 512         },
 513         {
 514                 /* DMARSx */
 515                 .start  = 0xfe009000,
 516                 .end    = 0xfe00900b,
 517                 .flags  = IORESOURCE_MEM,
 518         },
 519         {
 520                 .name   = "error_irq",
 521                 .start  = gic_spi(34),
 522                 .end    = gic_spi(34),
 523                 .flags  = IORESOURCE_IRQ,
 524         },
 525         {
 526                 /* IRQ for channels 0-5 */
 527                 .start  = gic_spi(28),
 528                 .end    = gic_spi(33),
 529                 .flags  = IORESOURCE_IRQ,
 530         },
 531 };
 532
 533 /* Resource order important! */
 534 static struct resource r8a7740_dmae1_resources[] = {
 535         {
 536                 /* Channel registers and DMAOR */
 537                 .start  = 0xfe018020,
 538                 .end    = 0xfe01828f,
 539                 .flags  = IORESOURCE_MEM,
 540         },
 541         {
 542                 /* DMARSx */
 543                 .start  = 0xfe019000,
 544                 .end    = 0xfe01900b,
 545                 .flags  = IORESOURCE_MEM,
 546         },
 547         {
 548                 .name   = "error_irq",
 549                 .start  = gic_spi(41),
 550                 .end    = gic_spi(41),
 551                 .flags  = IORESOURCE_IRQ,
 552         },
 553         {
 554                 /* IRQ for channels 0-5 */
 555                 .start  = gic_spi(35),
 556                 .end    = gic_spi(40),
 557                 .flags  = IORESOURCE_IRQ,
 558         },
 559 };
 560
 561 /* Resource order important! */
 562 static struct resource r8a7740_dmae2_resources[] = {
 563         {
 564                 /* Channel registers and DMAOR */
 565                 .start  = 0xfe028020,
 566                 .end    = 0xfe02828f,
 567                 .flags  = IORESOURCE_MEM,
 568         },
 569         {
 570                 /* DMARSx */
 571                 .start  = 0xfe029000,
 572                 .end    = 0xfe02900b,
 573                 .flags  = IORESOURCE_MEM,
 574         },
 575         {
 576                 .name   = "error_irq",
 577                 .start  = gic_spi(48),
 578                 .end    = gic_spi(48),
 579                 .flags  = IORESOURCE_IRQ,
 580         },
 581         {
 582                 /* IRQ for channels 0-5 */
 583                 .start  = gic_spi(42),
 584                 .end    = gic_spi(47),
 585                 .flags  = IORESOURCE_IRQ,
 586         },
 587 };
 588
 589 static struct platform_device dma0_device = {
 590         .name           = "sh-dma-engine",
 591         .id             = 0,
 592         .resource       = r8a7740_dmae0_resources,
 593         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 594         .dev            = {
 595                 .platform_data  = &dma_platform_data,
 596         },
 597 };
 598
 599 static struct platform_device dma1_device = {
 600         .name           = "sh-dma-engine",
 601         .id             = 1,
 602         .resource       = r8a7740_dmae1_resources,
 603         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 604         .dev            = {
 605                 .platform_data  = &dma_platform_data,
 606         },
 607 };
 608
 609 static struct platform_device dma2_device = {
 610         .name           = "sh-dma-engine",
 611         .id             = 2,
 612         .resource       = r8a7740_dmae2_resources,
 613         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 614         .dev            = {
 615                 .platform_data  = &dma_platform_data,
 616         },
 617 };
 618
 619 /* USB-DMAC */
 620 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 621         {
 622                 .offset = 0,
 623         }, {
 624                 .offset = 0x20,
 625         },
 626 };
 627
 628 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 629         {
 630                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 631                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 632         }, {
 633                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 634                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 635         },
 636 };
 637
 638 static struct sh_dmae_pdata usb_dma_platform_data = {
 639         .slave          = r8a7740_usb_dma_slaves,
 640         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 641         .channel        = r8a7740_usb_dma_channels,
 642         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 643         .ts_low_shift   = USBTS_LOW_SHIFT,
 644         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 645         .ts_high_shift  = USBTS_HI_SHIFT,
 646         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 647         .ts_shift       = dma_usbts_shift,
 648         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 649         .dmaor_init     = DMAOR_DME,
 650         .chcr_offset    = 0x14,
 651         .chcr_ie_bit    = 1 << 5,
 652         .dmaor_is_32bit = 1,
 653         .needs_tend_set = 1,
 654         .no_dmars       = 1,
 655         .slave_only     = 1,
 656 };
 657
 658 static struct resource r8a7740_usb_dma_resources[] = {
 659         {
 660                 /* Channel registers and DMAOR */
 661                 .start  = 0xe68a0020,
 662                 .end    = 0xe68a0064 - 1,
 663                 .flags  = IORESOURCE_MEM,
 664         },
 665         {
 666                 /* VCR/SWR/DMICR */
 667                 .start  = 0xe68a0000,
 668                 .end    = 0xe68a0014 - 1,
 669                 .flags  = IORESOURCE_MEM,
 670         },
 671         {
 672                 /* IRQ for channels */
 673                 .start  = gic_spi(49),
 674                 .end    = gic_spi(49),
 675                 .flags  = IORESOURCE_IRQ,
 676         },
 677 };
 678
 679 static struct platform_device usb_dma_device = {
 680         .name           = "sh-dma-engine",
 681         .id             = 3,
 682         .resource       = r8a7740_usb_dma_resources,
 683         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 684         .dev            = {
 685                 .platform_data  = &usb_dma_platform_data,
 686         },
 687 };
 688
 689 /* I2C */
 690 static struct resource i2c0_resources[] = {
 691         [0] = {
 692                 .name   = "IIC0",
 693                 .start  = 0xfff20000,
 694                 .end    = 0xfff20425 - 1,
 695                 .flags  = IORESOURCE_MEM,
 696         },
 697         [1] = {
 698                 .start  = gic_spi(201),
 699                 .end    = gic_spi(204),
 700                 .flags  = IORESOURCE_IRQ,
 701         },
 702 };
 703
 704 static struct resource i2c1_resources[] = {
 705         [0] = {
 706                 .name   = "IIC1",
 707                 .start  = 0xe6c20000,
 708                 .end    = 0xe6c20425 - 1,
 709                 .flags  = IORESOURCE_MEM,
 710         },
 711         [1] = {
 712                 .start  = gic_spi(70), /* IIC1_ALI1 */
 713                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 714                 .flags  = IORESOURCE_IRQ,
 715         },
 716 };
 717
 718 static struct platform_device i2c0_device = {
 719         .name           = "i2c-sh_mobile",
 720         .id             = 0,
 721         .resource       = i2c0_resources,
 722         .num_resources  = ARRAY_SIZE(i2c0_resources),
 723 };
 724
 725 static struct platform_device i2c1_device = {
 726         .name           = "i2c-sh_mobile",
 727         .id             = 1,
 728         .resource       = i2c1_resources,
 729         .num_resources  = ARRAY_SIZE(i2c1_resources),
 730 };
 731
 732 static struct resource pmu_resources[] = {
 733         [0] = {
 734                 .start  = gic_spi(83),
 735                 .end    = gic_spi(83),
 736                 .flags  = IORESOURCE_IRQ,
 737         },
 738 };
 739
 740 static struct platform_device pmu_device = {
 741         .name   = "arm-pmu",
 742         .id     = -1,
 743         .num_resources = ARRAY_SIZE(pmu_resources),
 744         .resource = pmu_resources,
 745 };
 746
 747 static struct platform_device *r8a7740_late_devices[] __initdata = {
 748         &i2c0_device,
 749         &i2c1_device,
 750         &dma0_device,
 751         &dma1_device,
 752         &dma2_device,
 753         &usb_dma_device,
 754         &pmu_device,
 755 };
 756
 757 /*
 758  * r8a7740 chip has lasting errata on MERAM buffer.
 759  * this is work-around for it.
 760  * see
 761  *      "Media RAM (MERAM)" on r8a7740 documentation
 762  */
 763 #define MEBUFCNTR       0xFE950098
 764 void r8a7740_meram_workaround(void)
 765 {
 766         void __iomem *reg;
 767
 768         reg = ioremap_nocache(MEBUFCNTR, 4);
 769         if (reg) {
 770                 iowrite32(0x01600164, reg);
 771                 iounmap(reg);
 772         }
 773 }
 774
 775 #define ICCR    0x0004
 776 #define ICSTART 0x0070
 777
 778 #define i2c_read(reg, offset)           ioread8(reg + offset)
 779 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 780
 781 /*
 782  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 783  * this is work-around for it.
 784  */
 785 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 786 {
 787         struct resource *res;
 788         void __iomem *reg;
 789
 790         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 791         if (unlikely(!res)) {
 792                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 793                 return;
 794         }
 795
 796         reg = ioremap(res->start, resource_size(res));
 797         if (unlikely(!reg)) {
 798                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 799                 return;
 800         }
 801
 802         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 803         i2c_read(reg, ICCR); /* dummy read */
 804
 805         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 806         i2c_read(reg, ICSTART); /* dummy read */
 807
 808         udelay(10);
 809
 810         i2c_write(reg, ICCR, 0x01);
 811         i2c_write(reg, ICSTART, 0x00);
 812
 813         udelay(10);
 814
 815         i2c_write(reg, ICCR, 0x10);
 816         udelay(10);
 817         i2c_write(reg, ICCR, 0x00);
 818         udelay(10);
 819         i2c_write(reg, ICCR, 0x10);
 820         udelay(10);
 821
 822         iounmap(reg);
 823 }
 824
 825 void __init r8a7740_add_standard_devices(void)
 826 {
 827         /* I2C work-around */
 828         r8a7740_i2c_workaround(&i2c0_device);
 829         r8a7740_i2c_workaround(&i2c1_device);
 830
 831         r8a7740_init_pm_domains();
 832
 833         /* add devices */
 834         platform_add_devices(r8a7740_early_devices,
 835                             ARRAY_SIZE(r8a7740_early_devices));
 836         platform_add_devices(r8a7740_devices_dt,
 837                             ARRAY_SIZE(r8a7740_devices_dt));
 838         platform_add_devices(r8a7740_late_devices,
 839                              ARRAY_SIZE(r8a7740_late_devices));
 840
 841         /* add devices to PM domain  */
 842
 843         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 844         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 845         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 846         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 847         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 848         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 849         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 850         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 851         rmobile_add_device_to_domain("A3SP",    &scif8_device);
 852         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 853 }
 854
 855 void __init r8a7740_add_early_devices(void)
 856 {
 857         early_platform_add_devices(r8a7740_early_devices,
 858                                    ARRAY_SIZE(r8a7740_early_devices));
 859         early_platform_add_devices(r8a7740_devices_dt,
 860                                    ARRAY_SIZE(r8a7740_devices_dt));
 861
 862         /* setup early console here as well */
 863         shmobile_setup_console();
 864 }
 865
 866 #ifdef CONFIG_USE_OF
 867
 868 void __init r8a7740_add_early_devices_dt(void)
 869 {
 870         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 871
 872         early_platform_add_devices(r8a7740_early_devices,
 873                                    ARRAY_SIZE(r8a7740_early_devices));
 874
 875         /* setup early console here as well */
 876         shmobile_setup_console();
 877 }
 878
 879 void __init r8a7740_add_standard_devices_dt(void)
 880 {
 881         platform_add_devices(r8a7740_devices_dt,
 882                             ARRAY_SIZE(r8a7740_devices_dt));
 883         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 884 }
 885
 886 void __init r8a7740_init_delay(void)
 887 {
 888         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 889 };
 890
 891 void __init r8a7740_init_irq_of(void)
 892 {
 893         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 894         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 895         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 896
 897         irqchip_init();
 898
 899         /* route signals to GIC */
 900         iowrite32(0x0, pfc_inta_ctrl);
 901
 902         /*
 903          * To mask the shared interrupt to SPI 149 we must ensure to set
 904          * PRIO *and* MASK. Else we run into IRQ floods when registering
 905          * the intc_irqpin devices
 906          */
 907         iowrite32(0x0, intc_prio_base + 0x0);
 908         iowrite32(0x0, intc_prio_base + 0x4);
 909         iowrite32(0x0, intc_prio_base + 0x8);
 910         iowrite32(0x0, intc_prio_base + 0xc);
 911         iowrite8(0xff, intc_msk_base + 0x0);
 912         iowrite8(0xff, intc_msk_base + 0x4);
 913         iowrite8(0xff, intc_msk_base + 0x8);
 914         iowrite8(0xff, intc_msk_base + 0xc);
 915
 916         iounmap(intc_prio_base);
 917         iounmap(intc_msk_base);
 918         iounmap(pfc_inta_ctrl);
 919 }
 920
 921 static void __init r8a7740_generic_init(void)
 922 {
 923         r8a7740_clock_init(0);
 924         r8a7740_add_standard_devices_dt();
 925 }
 926
 927 static const char *r8a7740_boards_compat_dt[] __initdata = {
 928         "renesas,r8a7740",
 929         NULL,
 930 };
 931
 932 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 933         .map_io         = r8a7740_map_io,
 934         .init_early     = r8a7740_init_delay,
 935         .init_irq       = r8a7740_init_irq_of,
 936         .init_machine   = r8a7740_generic_init,
 937         .dt_compat      = r8a7740_boards_compat_dt,
 938 MACHINE_END
 939
 940 #endif /* CONFIG_USE_OF */