2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_platform.h>
28 #include <linux/serial_sci.h>
29 #include <linux/sh_dma.h>
30 #include <linux/sh_timer.h>
31 #include <linux/platform_data/sh_ipmmu.h>
32 #include <mach/dma-register.h>
33 #include <mach/r8a7740.h>
34 #include <mach/pm-rmobile.h>
35 #include <mach/common.h>
36 #include <mach/irqs.h>
37 #include <asm/mach-types.h>
38 #include <asm/mach/map.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
42 static struct map_desc r8a7740_io_desc[] __initdata = {
45 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
48 .virtual = 0xe6000000,
49 .pfn = __phys_to_pfn(0xe6000000),
51 .type = MT_DEVICE_NONSHARED
53 #ifdef CONFIG_CACHE_L2X0
56 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
59 .virtual = 0xf0002000,
60 .pfn = __phys_to_pfn(0xf0100000),
62 .type = MT_DEVICE_NONSHARED
67 void __init r8a7740_map_io(void)
69 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
73 static struct resource r8a7740_pfc_resources[] = {
77 .flags = IORESOURCE_MEM,
82 .flags = IORESOURCE_MEM,
86 static struct platform_device r8a7740_pfc_device = {
87 .name = "pfc-r8a7740",
89 .resource = r8a7740_pfc_resources,
90 .num_resources = ARRAY_SIZE(r8a7740_pfc_resources),
93 void __init r8a7740_pinmux_init(void)
95 platform_device_register(&r8a7740_pfc_device);
98 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
102 static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
118 static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
124 .platform_data = &irqpin0_platform_data,
128 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
132 static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
148 static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
154 .platform_data = &irqpin1_platform_data,
158 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
162 static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
178 static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
184 .platform_data = &irqpin2_platform_data,
188 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
192 static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
208 static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
214 .platform_data = &irqpin3_platform_data,
219 static struct plat_sci_port scif0_platform_data = {
220 .mapbase = 0xe6c40000,
221 .flags = UPF_BOOT_AUTOCONF,
222 .scscr = SCSCR_RE | SCSCR_TE,
223 .scbrr_algo_id = SCBRR_ALGO_4,
225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
228 static struct platform_device scif0_device = {
232 .platform_data = &scif0_platform_data,
237 static struct plat_sci_port scif1_platform_data = {
238 .mapbase = 0xe6c50000,
239 .flags = UPF_BOOT_AUTOCONF,
240 .scscr = SCSCR_RE | SCSCR_TE,
241 .scbrr_algo_id = SCBRR_ALGO_4,
243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
246 static struct platform_device scif1_device = {
250 .platform_data = &scif1_platform_data,
255 static struct plat_sci_port scif2_platform_data = {
256 .mapbase = 0xe6c60000,
257 .flags = UPF_BOOT_AUTOCONF,
258 .scscr = SCSCR_RE | SCSCR_TE,
259 .scbrr_algo_id = SCBRR_ALGO_4,
261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
264 static struct platform_device scif2_device = {
268 .platform_data = &scif2_platform_data,
273 static struct plat_sci_port scif3_platform_data = {
274 .mapbase = 0xe6c70000,
275 .flags = UPF_BOOT_AUTOCONF,
276 .scscr = SCSCR_RE | SCSCR_TE,
277 .scbrr_algo_id = SCBRR_ALGO_4,
279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
282 static struct platform_device scif3_device = {
286 .platform_data = &scif3_platform_data,
291 static struct plat_sci_port scif4_platform_data = {
292 .mapbase = 0xe6c80000,
293 .flags = UPF_BOOT_AUTOCONF,
294 .scscr = SCSCR_RE | SCSCR_TE,
295 .scbrr_algo_id = SCBRR_ALGO_4,
297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
300 static struct platform_device scif4_device = {
304 .platform_data = &scif4_platform_data,
309 static struct plat_sci_port scif5_platform_data = {
310 .mapbase = 0xe6cb0000,
311 .flags = UPF_BOOT_AUTOCONF,
312 .scscr = SCSCR_RE | SCSCR_TE,
313 .scbrr_algo_id = SCBRR_ALGO_4,
315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
318 static struct platform_device scif5_device = {
322 .platform_data = &scif5_platform_data,
327 static struct plat_sci_port scif6_platform_data = {
328 .mapbase = 0xe6cc0000,
329 .flags = UPF_BOOT_AUTOCONF,
330 .scscr = SCSCR_RE | SCSCR_TE,
331 .scbrr_algo_id = SCBRR_ALGO_4,
333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
336 static struct platform_device scif6_device = {
340 .platform_data = &scif6_platform_data,
345 static struct plat_sci_port scif7_platform_data = {
346 .mapbase = 0xe6cd0000,
347 .flags = UPF_BOOT_AUTOCONF,
348 .scscr = SCSCR_RE | SCSCR_TE,
349 .scbrr_algo_id = SCBRR_ALGO_4,
351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
354 static struct platform_device scif7_device = {
358 .platform_data = &scif7_platform_data,
363 static struct plat_sci_port scifb_platform_data = {
364 .mapbase = 0xe6c30000,
365 .flags = UPF_BOOT_AUTOCONF,
366 .scscr = SCSCR_RE | SCSCR_TE,
367 .scbrr_algo_id = SCBRR_ALGO_4,
369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
372 static struct platform_device scifb_device = {
376 .platform_data = &scifb_platform_data,
381 static struct sh_timer_config cmt10_platform_data = {
383 .channel_offset = 0x10,
385 .clockevent_rating = 125,
386 .clocksource_rating = 125,
389 static struct resource cmt10_resources[] = {
394 .flags = IORESOURCE_MEM,
397 .start = gic_spi(58),
398 .flags = IORESOURCE_IRQ,
402 static struct platform_device cmt10_device = {
406 .platform_data = &cmt10_platform_data,
408 .resource = cmt10_resources,
409 .num_resources = ARRAY_SIZE(cmt10_resources),
413 static struct sh_timer_config tmu00_platform_data = {
415 .channel_offset = 0x4,
417 .clockevent_rating = 200,
420 static struct resource tmu00_resources[] = {
424 .end = 0xfff80014 - 1,
425 .flags = IORESOURCE_MEM,
428 .start = gic_spi(198),
429 .flags = IORESOURCE_IRQ,
433 static struct platform_device tmu00_device = {
437 .platform_data = &tmu00_platform_data,
439 .resource = tmu00_resources,
440 .num_resources = ARRAY_SIZE(tmu00_resources),
443 static struct sh_timer_config tmu01_platform_data = {
445 .channel_offset = 0x10,
447 .clocksource_rating = 200,
450 static struct resource tmu01_resources[] = {
454 .end = 0xfff80020 - 1,
455 .flags = IORESOURCE_MEM,
458 .start = gic_spi(199),
459 .flags = IORESOURCE_IRQ,
463 static struct platform_device tmu01_device = {
467 .platform_data = &tmu01_platform_data,
469 .resource = tmu01_resources,
470 .num_resources = ARRAY_SIZE(tmu01_resources),
473 static struct sh_timer_config tmu02_platform_data = {
475 .channel_offset = 0x1C,
477 .clocksource_rating = 200,
480 static struct resource tmu02_resources[] = {
484 .end = 0xfff8002C - 1,
485 .flags = IORESOURCE_MEM,
488 .start = gic_spi(200),
489 .flags = IORESOURCE_IRQ,
493 static struct platform_device tmu02_device = {
497 .platform_data = &tmu02_platform_data,
499 .resource = tmu02_resources,
500 .num_resources = ARRAY_SIZE(tmu02_resources),
503 /* IPMMUI (an IPMMU module for ICB/LMB) */
504 static struct resource ipmmu_resources[] = {
509 .flags = IORESOURCE_MEM,
513 static const char * const ipmmu_dev_names[] = {
514 "sh_mobile_lcdc_fb.0",
515 "sh_mobile_lcdc_fb.1",
519 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
520 .dev_names = ipmmu_dev_names,
521 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
524 static struct platform_device ipmmu_device = {
528 .platform_data = &ipmmu_platform_data,
530 .resource = ipmmu_resources,
531 .num_resources = ARRAY_SIZE(ipmmu_resources),
534 static struct platform_device *r8a7740_early_devices[] __initdata = {
556 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
558 .slave_id = SHDMA_SLAVE_SDHI0_TX,
560 .chcr = CHCR_TX(XMIT_SZ_16BIT),
563 .slave_id = SHDMA_SLAVE_SDHI0_RX,
565 .chcr = CHCR_RX(XMIT_SZ_16BIT),
568 .slave_id = SHDMA_SLAVE_SDHI1_TX,
570 .chcr = CHCR_TX(XMIT_SZ_16BIT),
573 .slave_id = SHDMA_SLAVE_SDHI1_RX,
575 .chcr = CHCR_RX(XMIT_SZ_16BIT),
578 .slave_id = SHDMA_SLAVE_SDHI2_TX,
580 .chcr = CHCR_TX(XMIT_SZ_16BIT),
583 .slave_id = SHDMA_SLAVE_SDHI2_RX,
585 .chcr = CHCR_RX(XMIT_SZ_16BIT),
588 .slave_id = SHDMA_SLAVE_FSIA_TX,
590 .chcr = CHCR_TX(XMIT_SZ_32BIT),
593 .slave_id = SHDMA_SLAVE_FSIA_RX,
595 .chcr = CHCR_RX(XMIT_SZ_32BIT),
598 .slave_id = SHDMA_SLAVE_FSIB_TX,
600 .chcr = CHCR_TX(XMIT_SZ_32BIT),
605 #define DMA_CHANNEL(a, b, c) \
610 .chclr_offset = (0x220 - 0x20) + a \
613 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
614 DMA_CHANNEL(0x00, 0, 0),
615 DMA_CHANNEL(0x10, 0, 8),
616 DMA_CHANNEL(0x20, 4, 0),
617 DMA_CHANNEL(0x30, 4, 8),
618 DMA_CHANNEL(0x50, 8, 0),
619 DMA_CHANNEL(0x60, 8, 8),
622 static struct sh_dmae_pdata dma_platform_data = {
623 .slave = r8a7740_dmae_slaves,
624 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
625 .channel = r8a7740_dmae_channels,
626 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
627 .ts_low_shift = TS_LOW_SHIFT,
628 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
629 .ts_high_shift = TS_HI_SHIFT,
630 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
631 .ts_shift = dma_ts_shift,
632 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
633 .dmaor_init = DMAOR_DME,
637 /* Resource order important! */
638 static struct resource r8a7740_dmae0_resources[] = {
640 /* Channel registers and DMAOR */
643 .flags = IORESOURCE_MEM,
649 .flags = IORESOURCE_MEM,
653 .start = gic_spi(34),
655 .flags = IORESOURCE_IRQ,
658 /* IRQ for channels 0-5 */
659 .start = gic_spi(28),
661 .flags = IORESOURCE_IRQ,
665 /* Resource order important! */
666 static struct resource r8a7740_dmae1_resources[] = {
668 /* Channel registers and DMAOR */
671 .flags = IORESOURCE_MEM,
677 .flags = IORESOURCE_MEM,
681 .start = gic_spi(41),
683 .flags = IORESOURCE_IRQ,
686 /* IRQ for channels 0-5 */
687 .start = gic_spi(35),
689 .flags = IORESOURCE_IRQ,
693 /* Resource order important! */
694 static struct resource r8a7740_dmae2_resources[] = {
696 /* Channel registers and DMAOR */
699 .flags = IORESOURCE_MEM,
705 .flags = IORESOURCE_MEM,
709 .start = gic_spi(48),
711 .flags = IORESOURCE_IRQ,
714 /* IRQ for channels 0-5 */
715 .start = gic_spi(42),
717 .flags = IORESOURCE_IRQ,
721 static struct platform_device dma0_device = {
722 .name = "sh-dma-engine",
724 .resource = r8a7740_dmae0_resources,
725 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
727 .platform_data = &dma_platform_data,
731 static struct platform_device dma1_device = {
732 .name = "sh-dma-engine",
734 .resource = r8a7740_dmae1_resources,
735 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
737 .platform_data = &dma_platform_data,
741 static struct platform_device dma2_device = {
742 .name = "sh-dma-engine",
744 .resource = r8a7740_dmae2_resources,
745 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
747 .platform_data = &dma_platform_data,
752 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
760 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
762 .slave_id = SHDMA_SLAVE_USBHS_TX,
763 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
765 .slave_id = SHDMA_SLAVE_USBHS_RX,
766 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
770 static struct sh_dmae_pdata usb_dma_platform_data = {
771 .slave = r8a7740_usb_dma_slaves,
772 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
773 .channel = r8a7740_usb_dma_channels,
774 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
775 .ts_low_shift = USBTS_LOW_SHIFT,
776 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
777 .ts_high_shift = USBTS_HI_SHIFT,
778 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
779 .ts_shift = dma_usbts_shift,
780 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
781 .dmaor_init = DMAOR_DME,
783 .chcr_ie_bit = 1 << 5,
790 static struct resource r8a7740_usb_dma_resources[] = {
792 /* Channel registers and DMAOR */
794 .end = 0xe68a0064 - 1,
795 .flags = IORESOURCE_MEM,
800 .end = 0xe68a0014 - 1,
801 .flags = IORESOURCE_MEM,
804 /* IRQ for channels */
805 .start = gic_spi(49),
807 .flags = IORESOURCE_IRQ,
811 static struct platform_device usb_dma_device = {
812 .name = "sh-dma-engine",
814 .resource = r8a7740_usb_dma_resources,
815 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
817 .platform_data = &usb_dma_platform_data,
822 static struct resource i2c0_resources[] = {
826 .end = 0xfff20425 - 1,
827 .flags = IORESOURCE_MEM,
830 .start = gic_spi(201),
832 .flags = IORESOURCE_IRQ,
836 static struct resource i2c1_resources[] = {
840 .end = 0xe6c20425 - 1,
841 .flags = IORESOURCE_MEM,
844 .start = gic_spi(70), /* IIC1_ALI1 */
845 .end = gic_spi(73), /* IIC1_DTEI1 */
846 .flags = IORESOURCE_IRQ,
850 static struct platform_device i2c0_device = {
851 .name = "i2c-sh_mobile",
853 .resource = i2c0_resources,
854 .num_resources = ARRAY_SIZE(i2c0_resources),
857 static struct platform_device i2c1_device = {
858 .name = "i2c-sh_mobile",
860 .resource = i2c1_resources,
861 .num_resources = ARRAY_SIZE(i2c1_resources),
864 static struct resource pmu_resources[] = {
866 .start = gic_spi(83),
868 .flags = IORESOURCE_IRQ,
872 static struct platform_device pmu_device = {
875 .num_resources = ARRAY_SIZE(pmu_resources),
876 .resource = pmu_resources,
879 static struct platform_device *r8a7740_late_devices[] __initdata = {
890 * r8a7740 chip has lasting errata on MERAM buffer.
891 * this is work-around for it.
893 * "Media RAM (MERAM)" on r8a7740 documentation
895 #define MEBUFCNTR 0xFE950098
896 void r8a7740_meram_workaround(void)
900 reg = ioremap_nocache(MEBUFCNTR, 4);
902 iowrite32(0x01600164, reg);
908 #define ICSTART 0x0070
910 #define i2c_read(reg, offset) ioread8(reg + offset)
911 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
914 * r8a7740 chip has lasting errata on I2C I/O pad reset.
915 * this is work-around for it.
917 static void r8a7740_i2c_workaround(struct platform_device *pdev)
919 struct resource *res;
922 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
923 if (unlikely(!res)) {
924 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
928 reg = ioremap(res->start, resource_size(res));
929 if (unlikely(!reg)) {
930 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
934 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
935 i2c_read(reg, ICCR); /* dummy read */
937 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
938 i2c_read(reg, ICSTART); /* dummy read */
942 i2c_write(reg, ICCR, 0x01);
943 i2c_write(reg, ICSTART, 0x00);
947 i2c_write(reg, ICCR, 0x10);
949 i2c_write(reg, ICCR, 0x00);
951 i2c_write(reg, ICCR, 0x10);
957 void __init r8a7740_add_standard_devices(void)
959 /* I2C work-around */
960 r8a7740_i2c_workaround(&i2c0_device);
961 r8a7740_i2c_workaround(&i2c1_device);
963 r8a7740_init_pm_domains();
966 platform_add_devices(r8a7740_early_devices,
967 ARRAY_SIZE(r8a7740_early_devices));
968 platform_add_devices(r8a7740_late_devices,
969 ARRAY_SIZE(r8a7740_late_devices));
971 /* add devices to PM domain */
973 rmobile_add_device_to_domain("A3SP", &scif0_device);
974 rmobile_add_device_to_domain("A3SP", &scif1_device);
975 rmobile_add_device_to_domain("A3SP", &scif2_device);
976 rmobile_add_device_to_domain("A3SP", &scif3_device);
977 rmobile_add_device_to_domain("A3SP", &scif4_device);
978 rmobile_add_device_to_domain("A3SP", &scif5_device);
979 rmobile_add_device_to_domain("A3SP", &scif6_device);
980 rmobile_add_device_to_domain("A3SP", &scif7_device);
981 rmobile_add_device_to_domain("A3SP", &scifb_device);
982 rmobile_add_device_to_domain("A3SP", &i2c1_device);
985 void __init r8a7740_add_early_devices(void)
987 early_platform_add_devices(r8a7740_early_devices,
988 ARRAY_SIZE(r8a7740_early_devices));
990 /* setup early console here as well */
991 shmobile_setup_console();
996 void __init r8a7740_add_early_devices_dt(void)
998 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1000 early_platform_add_devices(r8a7740_early_devices,
1001 ARRAY_SIZE(r8a7740_early_devices));
1003 /* setup early console here as well */
1004 shmobile_setup_console();
1007 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
1011 void __init r8a7740_add_standard_devices_dt(void)
1013 /* clocks are setup late during boot in the case of DT */
1014 r8a7740_clock_init(0);
1016 platform_add_devices(r8a7740_early_devices,
1017 ARRAY_SIZE(r8a7740_early_devices));
1019 of_platform_populate(NULL, of_default_bus_match_table,
1020 r8a7740_auxdata_lookup, NULL);
1023 static const char *r8a7740_boards_compat_dt[] __initdata = {
1028 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
1029 .map_io = r8a7740_map_io,
1030 .init_early = r8a7740_add_early_devices_dt,
1031 .init_irq = r8a7740_init_irq,
1032 .init_machine = r8a7740_add_standard_devices_dt,
1033 .dt_compat = r8a7740_boards_compat_dt,
1036 #endif /* CONFIG_USE_OF */