arch/arm/mach-shmobile/setup-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/delay.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/irqchip.h>
  26 #include <linux/irqchip/arm-gic.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_dma.h>
  32 #include <linux/sh_timer.h>
  33 #include <linux/platform_data/sh_ipmmu.h>
  34 #include <mach/dma-register.h>
  35 #include <mach/r8a7740.h>
  36 #include <mach/pm-rmobile.h>
  37 #include <mach/common.h>
  38 #include <mach/irqs.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/mach/map.h>
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/time.h>
  43
  44 static struct map_desc r8a7740_io_desc[] __initdata = {
  45          /*
  46           * for CPGA/INTC/PFC
  47           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
  48           */
  49         {
  50                 .virtual        = 0xe6000000,
  51                 .pfn            = __phys_to_pfn(0xe6000000),
  52                 .length         = 160 << 20,
  53                 .type           = MT_DEVICE_NONSHARED
  54         },
  55 #ifdef CONFIG_CACHE_L2X0
  56         /*
  57          * for l2x0_init()
  58          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
  59          */
  60         {
  61                 .virtual        = 0xf0002000,
  62                 .pfn            = __phys_to_pfn(0xf0100000),
  63                 .length         = PAGE_SIZE,
  64                 .type           = MT_DEVICE_NONSHARED
  65         },
  66 #endif
  67 };
  68
  69 void __init r8a7740_map_io(void)
  70 {
  71         iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
  72 }
  73
  74 /* PFC */
  75 static const struct resource pfc_resources[] = {
  76         DEFINE_RES_MEM(0xe6050000, 0x8000),
  77         DEFINE_RES_MEM(0xe605800c, 0x0020),
  78 };
  79
  80 void __init r8a7740_pinmux_init(void)
  81 {
  82         platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
  83                                         ARRAY_SIZE(pfc_resources));
  84 }
  85
  86 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
  87         .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
  88 };
  89
  90 static struct resource irqpin0_resources[] = {
  91         DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
  92         DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
  93         DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
  94         DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
  95         DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
  96         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
  97         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
  98         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
  99         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
 100         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
 101         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
 102         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
 103         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
 104 };
 105
 106 static struct platform_device irqpin0_device = {
 107         .name           = "renesas_intc_irqpin",
 108         .id             = 0,
 109         .resource       = irqpin0_resources,
 110         .num_resources  = ARRAY_SIZE(irqpin0_resources),
 111         .dev            = {
 112                 .platform_data  = &irqpin0_platform_data,
 113         },
 114 };
 115
 116 static struct renesas_intc_irqpin_config irqpin1_platform_data = {
 117         .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
 118 };
 119
 120 static struct resource irqpin1_resources[] = {
 121         DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
 122         DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
 123         DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
 124         DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
 125         DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
 126         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
 127         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
 128         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
 129         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
 130         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
 131         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
 132         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
 133         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
 134 };
 135
 136 static struct platform_device irqpin1_device = {
 137         .name           = "renesas_intc_irqpin",
 138         .id             = 1,
 139         .resource       = irqpin1_resources,
 140         .num_resources  = ARRAY_SIZE(irqpin1_resources),
 141         .dev            = {
 142                 .platform_data  = &irqpin1_platform_data,
 143         },
 144 };
 145
 146 static struct renesas_intc_irqpin_config irqpin2_platform_data = {
 147         .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
 148 };
 149
 150 static struct resource irqpin2_resources[] = {
 151         DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
 152         DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
 153         DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
 154         DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
 155         DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
 156         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
 157         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
 158         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
 159         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
 160         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
 161         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
 162         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
 163         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
 164 };
 165
 166 static struct platform_device irqpin2_device = {
 167         .name           = "renesas_intc_irqpin",
 168         .id             = 2,
 169         .resource       = irqpin2_resources,
 170         .num_resources  = ARRAY_SIZE(irqpin2_resources),
 171         .dev            = {
 172                 .platform_data  = &irqpin2_platform_data,
 173         },
 174 };
 175
 176 static struct renesas_intc_irqpin_config irqpin3_platform_data = {
 177         .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
 178 };
 179
 180 static struct resource irqpin3_resources[] = {
 181         DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
 182         DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
 183         DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
 184         DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
 185         DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
 186         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
 187         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
 188         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
 189         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
 190         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
 191         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
 192         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
 193         DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
 194 };
 195
 196 static struct platform_device irqpin3_device = {
 197         .name           = "renesas_intc_irqpin",
 198         .id             = 3,
 199         .resource       = irqpin3_resources,
 200         .num_resources  = ARRAY_SIZE(irqpin3_resources),
 201         .dev            = {
 202                 .platform_data  = &irqpin3_platform_data,
 203         },
 204 };
 205
 206 /* SCIF */
 207 #define R8A7740_SCIF(scif_type, index, baseaddr, irq)           \
 208 static struct plat_sci_port scif##index##_platform_data = {     \
 209         .type           = scif_type,                            \
 210         .flags          = UPF_BOOT_AUTOCONF,                    \
 211         .scscr          = SCSCR_RE | SCSCR_TE,                  \
 212 };                                                              \
 213                                                                 \
 214 static struct resource scif##index##_resources[] = {            \
 215         DEFINE_RES_MEM(baseaddr, 0x100),                        \
 216         DEFINE_RES_IRQ(irq),                                    \
 217 };                                                              \
 218                                                                 \
 219 static struct platform_device scif##index##_device = {          \
 220         .name           = "sh-sci",                             \
 221         .id             = index,                                \
 222         .resource       = scif##index##_resources,              \
 223         .num_resources  = ARRAY_SIZE(scif##index##_resources),  \
 224         .dev            = {                                     \
 225                 .platform_data  = &scif##index##_platform_data, \
 226         },                                                      \
 227 }
 228
 229 R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100));
 230 R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101));
 231 R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102));
 232 R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103));
 233 R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104));
 234 R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105));
 235 R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106));
 236 R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 237 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 238
 239 /* CMT */
 240 static struct sh_timer_config cmt1_platform_data = {
 241         .channels_mask = 0x3f,
 242 };
 243
 244 static struct resource cmt1_resources[] = {
 245         DEFINE_RES_MEM(0xe6138000, 0x170),
 246         DEFINE_RES_IRQ(gic_spi(58)),
 247 };
 248
 249 static struct platform_device cmt1_device = {
 250         .name           = "sh-cmt-48",
 251         .id             = 1,
 252         .dev = {
 253                 .platform_data  = &cmt1_platform_data,
 254         },
 255         .resource       = cmt1_resources,
 256         .num_resources  = ARRAY_SIZE(cmt1_resources),
 257 };
 258
 259 /* TMU */
 260 static struct sh_timer_config tmu00_platform_data = {
 261         .name = "TMU00",
 262         .channel_offset = 0x4,
 263         .timer_bit = 0,
 264         .clockevent_rating = 200,
 265 };
 266
 267 static struct resource tmu00_resources[] = {
 268         [0] = {
 269                 .name   = "TMU00",
 270                 .start  = 0xfff80008,
 271                 .end    = 0xfff80014 - 1,
 272                 .flags  = IORESOURCE_MEM,
 273         },
 274         [1] = {
 275                 .start  = gic_spi(198),
 276                 .flags  = IORESOURCE_IRQ,
 277         },
 278 };
 279
 280 static struct platform_device tmu00_device = {
 281         .name           = "sh_tmu",
 282         .id             = 0,
 283         .dev = {
 284                 .platform_data  = &tmu00_platform_data,
 285         },
 286         .resource       = tmu00_resources,
 287         .num_resources  = ARRAY_SIZE(tmu00_resources),
 288 };
 289
 290 static struct sh_timer_config tmu01_platform_data = {
 291         .name = "TMU01",
 292         .channel_offset = 0x10,
 293         .timer_bit = 1,
 294         .clocksource_rating = 200,
 295 };
 296
 297 static struct resource tmu01_resources[] = {
 298         [0] = {
 299                 .name   = "TMU01",
 300                 .start  = 0xfff80014,
 301                 .end    = 0xfff80020 - 1,
 302                 .flags  = IORESOURCE_MEM,
 303         },
 304         [1] = {
 305                 .start  = gic_spi(199),
 306                 .flags  = IORESOURCE_IRQ,
 307         },
 308 };
 309
 310 static struct platform_device tmu01_device = {
 311         .name           = "sh_tmu",
 312         .id             = 1,
 313         .dev = {
 314                 .platform_data  = &tmu01_platform_data,
 315         },
 316         .resource       = tmu01_resources,
 317         .num_resources  = ARRAY_SIZE(tmu01_resources),
 318 };
 319
 320 static struct sh_timer_config tmu02_platform_data = {
 321         .name = "TMU02",
 322         .channel_offset = 0x1C,
 323         .timer_bit = 2,
 324         .clocksource_rating = 200,
 325 };
 326
 327 static struct resource tmu02_resources[] = {
 328         [0] = {
 329                 .name   = "TMU02",
 330                 .start  = 0xfff80020,
 331                 .end    = 0xfff8002C - 1,
 332                 .flags  = IORESOURCE_MEM,
 333         },
 334         [1] = {
 335                 .start  = gic_spi(200),
 336                 .flags  = IORESOURCE_IRQ,
 337         },
 338 };
 339
 340 static struct platform_device tmu02_device = {
 341         .name           = "sh_tmu",
 342         .id             = 2,
 343         .dev = {
 344                 .platform_data  = &tmu02_platform_data,
 345         },
 346         .resource       = tmu02_resources,
 347         .num_resources  = ARRAY_SIZE(tmu02_resources),
 348 };
 349
 350 /* IPMMUI (an IPMMU module for ICB/LMB) */
 351 static struct resource ipmmu_resources[] = {
 352         [0] = {
 353                 .name   = "IPMMUI",
 354                 .start  = 0xfe951000,
 355                 .end    = 0xfe9510ff,
 356                 .flags  = IORESOURCE_MEM,
 357         },
 358 };
 359
 360 static const char * const ipmmu_dev_names[] = {
 361         "sh_mobile_lcdc_fb.0",
 362         "sh_mobile_lcdc_fb.1",
 363         "sh_mobile_ceu.0",
 364 };
 365
 366 static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
 367         .dev_names = ipmmu_dev_names,
 368         .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
 369 };
 370
 371 static struct platform_device ipmmu_device = {
 372         .name           = "ipmmu",
 373         .id             = -1,
 374         .dev = {
 375                 .platform_data = &ipmmu_platform_data,
 376         },
 377         .resource       = ipmmu_resources,
 378         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 379 };
 380
 381 static struct platform_device *r8a7740_devices_dt[] __initdata = {
 382         &scif0_device,
 383         &scif1_device,
 384         &scif2_device,
 385         &scif3_device,
 386         &scif4_device,
 387         &scif5_device,
 388         &scif6_device,
 389         &scif7_device,
 390         &scif8_device,
 391         &cmt1_device,
 392 };
 393
 394 static struct platform_device *r8a7740_early_devices[] __initdata = {
 395         &irqpin0_device,
 396         &irqpin1_device,
 397         &irqpin2_device,
 398         &irqpin3_device,
 399         &tmu00_device,
 400         &tmu01_device,
 401         &tmu02_device,
 402         &ipmmu_device,
 403 };
 404
 405 /* DMA */
 406 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
 407         {
 408                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 409                 .addr           = 0xe6850030,
 410                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 411                 .mid_rid        = 0xc1,
 412         }, {
 413                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 414                 .addr           = 0xe6850030,
 415                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 416                 .mid_rid        = 0xc2,
 417         }, {
 418                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 419                 .addr           = 0xe6860030,
 420                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 421                 .mid_rid        = 0xc9,
 422         }, {
 423                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 424                 .addr           = 0xe6860030,
 425                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 426                 .mid_rid        = 0xca,
 427         }, {
 428                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 429                 .addr           = 0xe6870030,
 430                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 431                 .mid_rid        = 0xcd,
 432         }, {
 433                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 434                 .addr           = 0xe6870030,
 435                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 436                 .mid_rid        = 0xce,
 437         }, {
 438                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
 439                 .addr           = 0xfe1f0024,
 440                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 441                 .mid_rid        = 0xb1,
 442         }, {
 443                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
 444                 .addr           = 0xfe1f0020,
 445                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 446                 .mid_rid        = 0xb2,
 447         }, {
 448                 .slave_id       = SHDMA_SLAVE_FSIB_TX,
 449                 .addr           = 0xfe1f0064,
 450                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 451                 .mid_rid        = 0xb5,
 452         }, {
 453                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 454                 .addr           = 0xe6bd0034,
 455                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 456                 .mid_rid        = 0xd1,
 457         }, {
 458                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 459                 .addr           = 0xe6bd0034,
 460                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 461                 .mid_rid        = 0xd2,
 462         },
 463 };
 464
 465 #define DMA_CHANNEL(a, b, c)                    \
 466 {                                               \
 467         .offset         = a,                    \
 468         .dmars          = b,                    \
 469         .dmars_bit      = c,                    \
 470         .chclr_offset   = (0x220 - 0x20) + a    \
 471 }
 472
 473 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
 474         DMA_CHANNEL(0x00, 0, 0),
 475         DMA_CHANNEL(0x10, 0, 8),
 476         DMA_CHANNEL(0x20, 4, 0),
 477         DMA_CHANNEL(0x30, 4, 8),
 478         DMA_CHANNEL(0x50, 8, 0),
 479         DMA_CHANNEL(0x60, 8, 8),
 480 };
 481
 482 static struct sh_dmae_pdata dma_platform_data = {
 483         .slave          = r8a7740_dmae_slaves,
 484         .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
 485         .channel        = r8a7740_dmae_channels,
 486         .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
 487         .ts_low_shift   = TS_LOW_SHIFT,
 488         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
 489         .ts_high_shift  = TS_HI_SHIFT,
 490         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
 491         .ts_shift       = dma_ts_shift,
 492         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
 493         .dmaor_init     = DMAOR_DME,
 494         .chclr_present  = 1,
 495 };
 496
 497 /* Resource order important! */
 498 static struct resource r8a7740_dmae0_resources[] = {
 499         {
 500                 /* Channel registers and DMAOR */
 501                 .start  = 0xfe008020,
 502                 .end    = 0xfe00828f,
 503                 .flags  = IORESOURCE_MEM,
 504         },
 505         {
 506                 /* DMARSx */
 507                 .start  = 0xfe009000,
 508                 .end    = 0xfe00900b,
 509                 .flags  = IORESOURCE_MEM,
 510         },
 511         {
 512                 .name   = "error_irq",
 513                 .start  = gic_spi(34),
 514                 .end    = gic_spi(34),
 515                 .flags  = IORESOURCE_IRQ,
 516         },
 517         {
 518                 /* IRQ for channels 0-5 */
 519                 .start  = gic_spi(28),
 520                 .end    = gic_spi(33),
 521                 .flags  = IORESOURCE_IRQ,
 522         },
 523 };
 524
 525 /* Resource order important! */
 526 static struct resource r8a7740_dmae1_resources[] = {
 527         {
 528                 /* Channel registers and DMAOR */
 529                 .start  = 0xfe018020,
 530                 .end    = 0xfe01828f,
 531                 .flags  = IORESOURCE_MEM,
 532         },
 533         {
 534                 /* DMARSx */
 535                 .start  = 0xfe019000,
 536                 .end    = 0xfe01900b,
 537                 .flags  = IORESOURCE_MEM,
 538         },
 539         {
 540                 .name   = "error_irq",
 541                 .start  = gic_spi(41),
 542                 .end    = gic_spi(41),
 543                 .flags  = IORESOURCE_IRQ,
 544         },
 545         {
 546                 /* IRQ for channels 0-5 */
 547                 .start  = gic_spi(35),
 548                 .end    = gic_spi(40),
 549                 .flags  = IORESOURCE_IRQ,
 550         },
 551 };
 552
 553 /* Resource order important! */
 554 static struct resource r8a7740_dmae2_resources[] = {
 555         {
 556                 /* Channel registers and DMAOR */
 557                 .start  = 0xfe028020,
 558                 .end    = 0xfe02828f,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         {
 562                 /* DMARSx */
 563                 .start  = 0xfe029000,
 564                 .end    = 0xfe02900b,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         {
 568                 .name   = "error_irq",
 569                 .start  = gic_spi(48),
 570                 .end    = gic_spi(48),
 571                 .flags  = IORESOURCE_IRQ,
 572         },
 573         {
 574                 /* IRQ for channels 0-5 */
 575                 .start  = gic_spi(42),
 576                 .end    = gic_spi(47),
 577                 .flags  = IORESOURCE_IRQ,
 578         },
 579 };
 580
 581 static struct platform_device dma0_device = {
 582         .name           = "sh-dma-engine",
 583         .id             = 0,
 584         .resource       = r8a7740_dmae0_resources,
 585         .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
 586         .dev            = {
 587                 .platform_data  = &dma_platform_data,
 588         },
 589 };
 590
 591 static struct platform_device dma1_device = {
 592         .name           = "sh-dma-engine",
 593         .id             = 1,
 594         .resource       = r8a7740_dmae1_resources,
 595         .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
 596         .dev            = {
 597                 .platform_data  = &dma_platform_data,
 598         },
 599 };
 600
 601 static struct platform_device dma2_device = {
 602         .name           = "sh-dma-engine",
 603         .id             = 2,
 604         .resource       = r8a7740_dmae2_resources,
 605         .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
 606         .dev            = {
 607                 .platform_data  = &dma_platform_data,
 608         },
 609 };
 610
 611 /* USB-DMAC */
 612 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
 613         {
 614                 .offset = 0,
 615         }, {
 616                 .offset = 0x20,
 617         },
 618 };
 619
 620 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
 621         {
 622                 .slave_id       = SHDMA_SLAVE_USBHS_TX,
 623                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 624         }, {
 625                 .slave_id       = SHDMA_SLAVE_USBHS_RX,
 626                 .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
 627         },
 628 };
 629
 630 static struct sh_dmae_pdata usb_dma_platform_data = {
 631         .slave          = r8a7740_usb_dma_slaves,
 632         .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
 633         .channel        = r8a7740_usb_dma_channels,
 634         .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
 635         .ts_low_shift   = USBTS_LOW_SHIFT,
 636         .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
 637         .ts_high_shift  = USBTS_HI_SHIFT,
 638         .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
 639         .ts_shift       = dma_usbts_shift,
 640         .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
 641         .dmaor_init     = DMAOR_DME,
 642         .chcr_offset    = 0x14,
 643         .chcr_ie_bit    = 1 << 5,
 644         .dmaor_is_32bit = 1,
 645         .needs_tend_set = 1,
 646         .no_dmars       = 1,
 647         .slave_only     = 1,
 648 };
 649
 650 static struct resource r8a7740_usb_dma_resources[] = {
 651         {
 652                 /* Channel registers and DMAOR */
 653                 .start  = 0xe68a0020,
 654                 .end    = 0xe68a0064 - 1,
 655                 .flags  = IORESOURCE_MEM,
 656         },
 657         {
 658                 /* VCR/SWR/DMICR */
 659                 .start  = 0xe68a0000,
 660                 .end    = 0xe68a0014 - 1,
 661                 .flags  = IORESOURCE_MEM,
 662         },
 663         {
 664                 /* IRQ for channels */
 665                 .start  = gic_spi(49),
 666                 .end    = gic_spi(49),
 667                 .flags  = IORESOURCE_IRQ,
 668         },
 669 };
 670
 671 static struct platform_device usb_dma_device = {
 672         .name           = "sh-dma-engine",
 673         .id             = 3,
 674         .resource       = r8a7740_usb_dma_resources,
 675         .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
 676         .dev            = {
 677                 .platform_data  = &usb_dma_platform_data,
 678         },
 679 };
 680
 681 /* I2C */
 682 static struct resource i2c0_resources[] = {
 683         [0] = {
 684                 .name   = "IIC0",
 685                 .start  = 0xfff20000,
 686                 .end    = 0xfff20425 - 1,
 687                 .flags  = IORESOURCE_MEM,
 688         },
 689         [1] = {
 690                 .start  = gic_spi(201),
 691                 .end    = gic_spi(204),
 692                 .flags  = IORESOURCE_IRQ,
 693         },
 694 };
 695
 696 static struct resource i2c1_resources[] = {
 697         [0] = {
 698                 .name   = "IIC1",
 699                 .start  = 0xe6c20000,
 700                 .end    = 0xe6c20425 - 1,
 701                 .flags  = IORESOURCE_MEM,
 702         },
 703         [1] = {
 704                 .start  = gic_spi(70), /* IIC1_ALI1 */
 705                 .end    = gic_spi(73), /* IIC1_DTEI1 */
 706                 .flags  = IORESOURCE_IRQ,
 707         },
 708 };
 709
 710 static struct platform_device i2c0_device = {
 711         .name           = "i2c-sh_mobile",
 712         .id             = 0,
 713         .resource       = i2c0_resources,
 714         .num_resources  = ARRAY_SIZE(i2c0_resources),
 715 };
 716
 717 static struct platform_device i2c1_device = {
 718         .name           = "i2c-sh_mobile",
 719         .id             = 1,
 720         .resource       = i2c1_resources,
 721         .num_resources  = ARRAY_SIZE(i2c1_resources),
 722 };
 723
 724 static struct resource pmu_resources[] = {
 725         [0] = {
 726                 .start  = gic_spi(83),
 727                 .end    = gic_spi(83),
 728                 .flags  = IORESOURCE_IRQ,
 729         },
 730 };
 731
 732 static struct platform_device pmu_device = {
 733         .name   = "arm-pmu",
 734         .id     = -1,
 735         .num_resources = ARRAY_SIZE(pmu_resources),
 736         .resource = pmu_resources,
 737 };
 738
 739 static struct platform_device *r8a7740_late_devices[] __initdata = {
 740         &i2c0_device,
 741         &i2c1_device,
 742         &dma0_device,
 743         &dma1_device,
 744         &dma2_device,
 745         &usb_dma_device,
 746         &pmu_device,
 747 };
 748
 749 /*
 750  * r8a7740 chip has lasting errata on MERAM buffer.
 751  * this is work-around for it.
 752  * see
 753  *      "Media RAM (MERAM)" on r8a7740 documentation
 754  */
 755 #define MEBUFCNTR       0xFE950098
 756 void __init r8a7740_meram_workaround(void)
 757 {
 758         void __iomem *reg;
 759
 760         reg = ioremap_nocache(MEBUFCNTR, 4);
 761         if (reg) {
 762                 iowrite32(0x01600164, reg);
 763                 iounmap(reg);
 764         }
 765 }
 766
 767 #define ICCR    0x0004
 768 #define ICSTART 0x0070
 769
 770 #define i2c_read(reg, offset)           ioread8(reg + offset)
 771 #define i2c_write(reg, offset, data)    iowrite8(data, reg + offset)
 772
 773 /*
 774  * r8a7740 chip has lasting errata on I2C I/O pad reset.
 775  * this is work-around for it.
 776  */
 777 static void r8a7740_i2c_workaround(struct platform_device *pdev)
 778 {
 779         struct resource *res;
 780         void __iomem *reg;
 781
 782         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 783         if (unlikely(!res)) {
 784                 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
 785                 return;
 786         }
 787
 788         reg = ioremap(res->start, resource_size(res));
 789         if (unlikely(!reg)) {
 790                 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
 791                 return;
 792         }
 793
 794         i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
 795         i2c_read(reg, ICCR); /* dummy read */
 796
 797         i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
 798         i2c_read(reg, ICSTART); /* dummy read */
 799
 800         udelay(10);
 801
 802         i2c_write(reg, ICCR, 0x01);
 803         i2c_write(reg, ICSTART, 0x00);
 804
 805         udelay(10);
 806
 807         i2c_write(reg, ICCR, 0x10);
 808         udelay(10);
 809         i2c_write(reg, ICCR, 0x00);
 810         udelay(10);
 811         i2c_write(reg, ICCR, 0x10);
 812         udelay(10);
 813
 814         iounmap(reg);
 815 }
 816
 817 void __init r8a7740_add_standard_devices(void)
 818 {
 819         /* I2C work-around */
 820         r8a7740_i2c_workaround(&i2c0_device);
 821         r8a7740_i2c_workaround(&i2c1_device);
 822
 823         r8a7740_init_pm_domains();
 824
 825         /* add devices */
 826         platform_add_devices(r8a7740_early_devices,
 827                             ARRAY_SIZE(r8a7740_early_devices));
 828         platform_add_devices(r8a7740_devices_dt,
 829                             ARRAY_SIZE(r8a7740_devices_dt));
 830         platform_add_devices(r8a7740_late_devices,
 831                              ARRAY_SIZE(r8a7740_late_devices));
 832
 833         /* add devices to PM domain  */
 834
 835         rmobile_add_device_to_domain("A3SP",    &scif0_device);
 836         rmobile_add_device_to_domain("A3SP",    &scif1_device);
 837         rmobile_add_device_to_domain("A3SP",    &scif2_device);
 838         rmobile_add_device_to_domain("A3SP",    &scif3_device);
 839         rmobile_add_device_to_domain("A3SP",    &scif4_device);
 840         rmobile_add_device_to_domain("A3SP",    &scif5_device);
 841         rmobile_add_device_to_domain("A3SP",    &scif6_device);
 842         rmobile_add_device_to_domain("A3SP",    &scif7_device);
 843         rmobile_add_device_to_domain("A3SP",    &scif8_device);
 844         rmobile_add_device_to_domain("A3SP",    &i2c1_device);
 845 }
 846
 847 void __init r8a7740_add_early_devices(void)
 848 {
 849         early_platform_add_devices(r8a7740_early_devices,
 850                                    ARRAY_SIZE(r8a7740_early_devices));
 851         early_platform_add_devices(r8a7740_devices_dt,
 852                                    ARRAY_SIZE(r8a7740_devices_dt));
 853
 854         /* setup early console here as well */
 855         shmobile_setup_console();
 856 }
 857
 858 #ifdef CONFIG_USE_OF
 859
 860 void __init r8a7740_add_standard_devices_dt(void)
 861 {
 862         platform_add_devices(r8a7740_devices_dt,
 863                             ARRAY_SIZE(r8a7740_devices_dt));
 864         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 865 }
 866
 867 void __init r8a7740_init_delay(void)
 868 {
 869         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 870 };
 871
 872 void __init r8a7740_init_irq_of(void)
 873 {
 874         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
 875         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
 876         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 877
 878         irqchip_init();
 879
 880         /* route signals to GIC */
 881         iowrite32(0x0, pfc_inta_ctrl);
 882
 883         /*
 884          * To mask the shared interrupt to SPI 149 we must ensure to set
 885          * PRIO *and* MASK. Else we run into IRQ floods when registering
 886          * the intc_irqpin devices
 887          */
 888         iowrite32(0x0, intc_prio_base + 0x0);
 889         iowrite32(0x0, intc_prio_base + 0x4);
 890         iowrite32(0x0, intc_prio_base + 0x8);
 891         iowrite32(0x0, intc_prio_base + 0xc);
 892         iowrite8(0xff, intc_msk_base + 0x0);
 893         iowrite8(0xff, intc_msk_base + 0x4);
 894         iowrite8(0xff, intc_msk_base + 0x8);
 895         iowrite8(0xff, intc_msk_base + 0xc);
 896
 897         iounmap(intc_prio_base);
 898         iounmap(intc_msk_base);
 899         iounmap(pfc_inta_ctrl);
 900 }
 901
 902 static void __init r8a7740_generic_init(void)
 903 {
 904         r8a7740_clock_init(0);
 905         r8a7740_add_standard_devices_dt();
 906 }
 907
 908 static const char *r8a7740_boards_compat_dt[] __initdata = {
 909         "renesas,r8a7740",
 910         NULL,
 911 };
 912
 913 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
 914         .map_io         = r8a7740_map_io,
 915         .init_early     = r8a7740_init_delay,
 916         .init_irq       = r8a7740_init_irq_of,
 917         .init_machine   = r8a7740_generic_init,
 918         .dt_compat      = r8a7740_boards_compat_dt,
 919 MACHINE_END
 920
 921 #endif /* CONFIG_USE_OF */