arch/arm/mach-shmobile/clock-r7s72100.c

   1 /*
   2  * r7a72100 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2012  Phil Edworthy
   6  * Copyright (C) 2011  Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/io.h>
  20 #include <linux/sh_clk.h>
  21 #include <linux/clkdev.h>
  22
  23 #include "common.h"
  24 #include "r7s72100.h"
  25
  26 /* Frequency Control Registers */
  27 #define FRQCR           0xfcfe0010
  28 #define FRQCR2          0xfcfe0014
  29 /* Standby Control Registers */
  30 #define STBCR3          0xfcfe0420
  31 #define STBCR4          0xfcfe0424
  32 #define STBCR7          0xfcfe0430
  33 #define STBCR9          0xfcfe0438
  34 #define STBCR10         0xfcfe043c
  35
  36 #define PLL_RATE 30
  37
  38 static struct clk_mapping cpg_mapping = {
  39         .phys   = 0xfcfe0000,
  40         .len    = 0x1000,
  41 };
  42
  43 /* Fixed 32 KHz root clock for RTC */
  44 static struct clk r_clk = {
  45         .rate           = 32768,
  46 };
  47
  48 /*
  49  * Default rate for the root input clock, reset this with clk_set_rate()
  50  * from the platform code.
  51  */
  52 static struct clk extal_clk = {
  53         .rate           = 13330000,
  54         .mapping        = &cpg_mapping,
  55 };
  56
  57 static unsigned long pll_recalc(struct clk *clk)
  58 {
  59         return clk->parent->rate * PLL_RATE;
  60 }
  61
  62 static struct sh_clk_ops pll_clk_ops = {
  63         .recalc         = pll_recalc,
  64 };
  65
  66 static struct clk pll_clk = {
  67         .ops            = &pll_clk_ops,
  68         .parent         = &extal_clk,
  69         .flags          = CLK_ENABLE_ON_INIT,
  70 };
  71
  72 static unsigned long bus_recalc(struct clk *clk)
  73 {
  74         return clk->parent->rate / 3;
  75 }
  76
  77 static struct sh_clk_ops bus_clk_ops = {
  78         .recalc         = bus_recalc,
  79 };
  80
  81 static struct clk bus_clk = {
  82         .ops            = &bus_clk_ops,
  83         .parent         = &pll_clk,
  84         .flags          = CLK_ENABLE_ON_INIT,
  85 };
  86
  87 static unsigned long peripheral0_recalc(struct clk *clk)
  88 {
  89         return clk->parent->rate / 12;
  90 }
  91
  92 static struct sh_clk_ops peripheral0_clk_ops = {
  93         .recalc         = peripheral0_recalc,
  94 };
  95
  96 static struct clk peripheral0_clk = {
  97         .ops            = &peripheral0_clk_ops,
  98         .parent         = &pll_clk,
  99         .flags          = CLK_ENABLE_ON_INIT,
 100 };
 101
 102 static unsigned long peripheral1_recalc(struct clk *clk)
 103 {
 104         return clk->parent->rate / 6;
 105 }
 106
 107 static struct sh_clk_ops peripheral1_clk_ops = {
 108         .recalc         = peripheral1_recalc,
 109 };
 110
 111 static struct clk peripheral1_clk = {
 112         .ops            = &peripheral1_clk_ops,
 113         .parent         = &pll_clk,
 114         .flags          = CLK_ENABLE_ON_INIT,
 115 };
 116
 117 struct clk *main_clks[] = {
 118         &r_clk,
 119         &extal_clk,
 120         &pll_clk,
 121         &bus_clk,
 122         &peripheral0_clk,
 123         &peripheral1_clk,
 124 };
 125
 126 static int div2[] = { 1, 3, 0, 3 }; /* 1, 2/3, reserve, 1/3 */
 127 static int multipliers[] = { 1, 2, 1, 1 };
 128
 129 static struct clk_div_mult_table div4_div_mult_table = {
 130         .divisors = div2,
 131         .nr_divisors = ARRAY_SIZE(div2),
 132         .multipliers = multipliers,
 133         .nr_multipliers = ARRAY_SIZE(multipliers),
 134 };
 135
 136 static struct clk_div4_table div4_table = {
 137         .div_mult_table = &div4_div_mult_table,
 138 };
 139
 140 enum { DIV4_I,
 141         DIV4_NR };
 142
 143 #define DIV4(_reg, _bit, _mask, _flags) \
 144         SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 145
 146 /* The mask field specifies the div2 entries that are valid */
 147 struct clk div4_clks[DIV4_NR] = {
 148         [DIV4_I]  = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
 149                                         | CLK_ENABLE_ON_INIT),
 150 };
 151
 152 enum {
 153         MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
 154         MSTP97, MSTP96, MSTP95, MSTP94,
 155         MSTP74,
 156         MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
 157         MSTP33, MSTP_NR
 158 };
 159
 160 static struct clk mstp_clks[MSTP_NR] = {
 161         [MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
 162         [MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
 163         [MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
 164         [MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
 165         [MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
 166         [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
 167         [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
 168         [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
 169         [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
 170         [MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
 171         [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
 172         [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
 173         [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
 174         [MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
 175         [MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
 176         [MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
 177         [MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
 178         [MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
 179         [MSTP33] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 3, 0), /* MTU2 */
 180 };
 181
 182 static struct clk_lookup lookups[] = {
 183         /* main clocks */
 184         CLKDEV_CON_ID("rclk", &r_clk),
 185         CLKDEV_CON_ID("extal", &extal_clk),
 186         CLKDEV_CON_ID("pll_clk", &pll_clk),
 187         CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
 188
 189         /* DIV4 clocks */
 190         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 191
 192         /* MSTP clocks */
 193         CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
 194         CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
 195         CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
 196         CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
 197         CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
 198         CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
 199
 200         /* ICK */
 201         CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
 202         CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
 203         CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
 204         CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
 205         CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
 206         CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
 207         CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
 208         CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
 209         CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
 210 };
 211
 212 void __init r7s72100_clock_init(void)
 213 {
 214         int k, ret = 0;
 215
 216         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 217                 ret = clk_register(main_clks[k]);
 218
 219         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 220
 221         if (!ret)
 222                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 223
 224         if (!ret)
 225                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 226
 227         if (!ret)
 228                 shmobile_clk_init();
 229         else
 230                 panic("failed to setup rza1 clocks\n");
 231 }