arch/arm/mach-sc/board-coreprimelite.c

   1 /*
   2  * Copyright (C) 2014 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/delay.h>
  18 #include <linux/export.h>
  19 #include <linux/irqchip/arm-gic.h>
  20 #include <linux/input.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/setup.h>
  24 #include <asm/mach/time.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/localtimer.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/of.h>
  32 #include <linux/of_address.h>
  33 #include <linux/clocksource.h>
  34 #include <linux/clk-provider.h>
  35 #include <soc/sprd/hardware.h>
  36 #include <linux/i2c.h>
  37 #if (defined(CONFIG_INPUT_LIS3DH_I2C) || defined(CONFIG_INPUT_LIS3DH_I2C_MODULE))
  38 #include <linux/i2c/lis3dh.h>
  39 #endif
  40 #if (defined(CONFIG_INPUT_LTR558_I2C) || defined(CONFIG_INPUT_LTR558_I2C_MODULE))
  41 #include <linux/i2c/ltr_558als.h>
  42 #endif
  43 #if (defined(CONFIG_TOUCHSCREEN_MSG2138) || defined(CONFIG_TOUCHSCREEN_MSG2138_MODULE))
  44 #include <linux/i2c/msg2138.h>
  45 #endif
  46 #include <linux/spi/spi.h>
  47 #include <linux/gpio.h>
  48 #include <soc/sprd/board.h>
  49 #include <soc/sprd/serial_sprd.h>
  50 #include <soc/sprd/adi.h>
  51 #include <soc/sprd/adc.h>
  52 #include <soc/sprd/pinmap.h>
  53 #include <linux/irq.h>
  54 #include <linux/input/matrix_keypad.h>
  55
  56 #include <soc/sprd/sci.h>
  57 #include <soc/sprd/kpd.h>
  58 #include <soc/sprd/sci_glb_regs.h>
  59
  60 #if (defined(CONFIG_INV_MPU_IIO) || defined(CONFIG_INV_MPU_IIO_MODULE))
  61 #include <linux/mpu.h>
  62 #endif
  63 #if (defined(CONFIG_SENSORS_AK8975) || defined(CONFIG_SENSORS_AK8975_MODULE))
  64 #include <linux/akm8975.h>
  65 #endif
  66
  67
  68 /* IRQ's for the multi sensor board */
  69 #define MPUIRQ_GPIO 212
  70 #include <linux/regulator/consumer.h>
  71 #include <soc/sprd/regulator.h>
  72 #if (defined(CONFIG_TOUCHSCREEN_FOCALTECH) || defined(CONFIG_TOUCHSCREEN_FOCALTECH_MODULE))
  73 #include <linux/i2c/focaltech.h>
  74 #endif
  75
  76 #if (defined(CONFIG_KEYBOARD_SC) || defined (CONFIG_KEYBOARD_SC_MODULE))
  77 #include <linux/input/matrix_keypad.h>
  78 #include <soc/sprd/kpd.h>
  79 #endif
  80 #if (defined(CONFIG_KEYBOARD_GPIO) || defined (CONFIG_KEYBOARD_GPIO_MODULE))
  81 #include <linux/gpio_keys.h>
  82 #endif
  83 #if (defined(CONFIG_KEYBOARD_SPRD_EIC) || defined(CONFIG_KEYBOARD_SPRD_EIC_MODULE))
  84 #include <linux/sprd_eic_keys.h>
  85 #endif
  86 #if (defined(CONFIG_BACKLIGHT_SPRD_PWM) || defined(CONFIG_BACKLIGHT_SPRD_PWM_MODULE))
  87 #include <linux/sprd_pwm_bl.h>
  88 #endif
  89 #if (defined(CONFIG_INPUT_HEADSET_SPRD_SC2723) || defined(CONFIG_INPUT_HEADSET_SPRD_SC2723_MODULE))
  90 #include <linux/headset_sprd_sc2723.h>
  91 #endif
  92 extern void bluesleep_setup_uart_port(struct platform_device *uart_dev);
  93 extern void __init sci_reserve(void);
  94 extern void __init sci_map_io(void);
  95 extern void __init sci_init_irq(void);
  96 extern void __init sci_timer_init(void);
  97 extern int __init sci_clock_init(void);
  98 extern int __init sci_regulator_init(void);
  99
 100 struct class *sec_class;
 101 EXPORT_SYMBOL(sec_class);
 102 int __init __clock_init_early(void)
 103 {
 104 #if !defined(CONFIG_ARCH_SCX15)
 105         pr_info("ahb ctl0 %08x, ctl2 %0x8 glb aon apb0 %08x aon apb1 %08x clk_en %08x\n",
 106                 sci_glb_raw_read(REG_AP_AHB_AHB_EB),
 107                 sci_glb_raw_read(REG_AP_AHB_AHB_RST),
 108                 sci_glb_raw_read(REG_AON_APB_APB_EB0),
 109                 sci_glb_raw_read(REG_AON_APB_APB_EB1),
 110                 sci_glb_raw_read(REG_AON_CLK_PUB_AHB_CFG));
 111 #endif
 112
 113         sci_glb_clr(REG_AP_AHB_AHB_EB,
 114                 BIT_BUSMON2_EB          |
 115                 BIT_BUSMON1_EB          |
 116                 BIT_BUSMON0_EB          |
 117                 BIT_SPINLOCK_EB         |
 118 #if !defined(CONFIG_ARCH_SCX35L)
 119                 BIT_GPS_EB              |
 120 #endif
 121                 BIT_EMMC_EB             |
 122                 BIT_SDIO2_EB            |
 123                 BIT_SDIO1_EB            |
 124                 BIT_SDIO0_EB            |
 125                 BIT_DRM_EB              |
 126                 BIT_NFC_EB              |
 127                 BIT_DMA_EB              |
 128                 BIT_USB_EB              |
 129 #if !defined(CONFIG_ARCH_SCX35L)
 130                 BIT_GSP_EB              |
 131                 BIT_DISPC1_EB           |
 132 #endif
 133                 0);
 134         sci_glb_clr(REG_AP_APB_APB_EB,
 135                 BIT_INTC3_EB            |
 136                 BIT_INTC2_EB            |
 137                 BIT_INTC1_EB            |
 138                 BIT_IIS1_EB             |
 139                 BIT_UART2_EB            |
 140                 BIT_UART0_EB            |
 141                 BIT_SPI1_EB             |
 142                 BIT_SPI0_EB             |
 143                 BIT_IIS0_EB             |
 144                 BIT_I2C0_EB             |
 145                 BIT_SPI2_EB             |
 146                 BIT_UART3_EB            |
 147                 0);
 148         sci_glb_clr(REG_AON_APB_APB_RTC_EB,
 149                 BIT_KPD_RTC_EB          |
 150                 BIT_KPD_EB              |
 151                 BIT_EFUSE_EB            |
 152                 0);
 153
 154         sci_glb_clr(REG_AON_APB_APB_EB0,
 155                 BIT_AUDIF_EB                    |
 156                 BIT_VBC_EB                      |
 157                 BIT_PWM3_EB                     |
 158                 BIT_PWM1_EB                     |
 159                 0);
 160         sci_glb_clr(REG_AON_APB_APB_EB1,
 161                 BIT_AUX1_EB                     |
 162                 BIT_AUX0_EB                     |
 163                 0);
 164         printk("sc clock module early init ok\n");
 165         return 0;
 166 }
 167
 168 static inline int __sci_get_chip_id(void)
 169 {
 170         return __raw_readl(CHIP_ID_LOW_REG);
 171 }
 172
 173 const struct of_device_id of_sprd_default_bus_match_table[] = {
 174         { .compatible = "simple-bus", },
 175         { .compatible = "sprd,adi-bus", },
 176         {}
 177 };
 178
 179 static struct of_dev_auxdata of_sprd_default_bus_lookup[] = {
 180          { .compatible = "sprd,sprd_backlight",  .name = "sprd_backlight" },
 181 #if(defined(CONFIG_BACKLIGHT_SPRD_PWM)||defined(CONFIG_BACKLIGHT_SPRD_PWM_MODULE))
 182         { .compatible = "sprd,sprd_pwm_bl",  .name = "sprd_pwm_bl" },
 183 #endif
 184 #if (defined(CONFIG_KEYBOARD_SC) || defined(CONFIG_KEYBOARD_SC_MODULE))
 185         {.compatible = "sprd,sci-keypad", .name = "sci-keypad" },
 186 #endif
 187 #if (defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE))
 188         {.compatible = "gpio-keys", .name = "gpio-keys" },
 189 #endif
 190 #if (defined(CONFIG_KEYBOARD_SPRD_EIC) || defined(CONFIG_KEYBOARD_SPRD_EIC_MODULE))
 191         {.compatible = "sprd,sprd-eic-keys", .name = "sprd-eic-keys" },
 192 #endif
 193 #if (defined(CONFIG_INPUT_HEADSET_SPRD_SC2723) || defined(CONFIG_INPUT_HEADSET_SPRD_SC2723_MODULE))
 194         { .compatible = "sprd,headset_sprd_sc2723",  .name = "headset_sprd_sc2723" },
 195 #endif
 196         {}
 197 };
 198
 199 struct iotable_sprd io_addr_sprd;
 200 EXPORT_SYMBOL(io_addr_sprd);
 201
 202 int iotable_build()
 203 {
 204         struct device_node *np;
 205         struct resource res;
 206
 207 #define ADD_SPRD_DEVICE(compat, id)                     \
 208 do {                                                    \
 209         np = of_find_compatible_node(NULL, NULL, compat);\
 210         if (of_can_translate_address(np)) {             \
 211                 of_address_to_resource(np, 0, &res);    \
 212                 io_addr_sprd.id.paddr = res.start;      \
 213                 io_addr_sprd.id.length =                \
 214                         resource_size(&res);            \
 215                 io_addr_sprd.id.vaddr =                 \
 216                 ioremap_nocache(res.start, io_addr_sprd.id.length);\
 217                 pr_debug("sprd io map: phys=%08x virt=%08x size=%08x\n", \
 218         io_addr_sprd.id.paddr, io_addr_sprd.id.vaddr, io_addr_sprd.id.length);\
 219         }                                               \
 220 } while (0)
 221 #define ADD_SPRD_DEVICE_BY_NAME(name, id)               \
 222 do {                                                    \
 223         np = of_find_node_by_name(NULL, name);          \
 224         if (of_can_translate_address(np)) {             \
 225                 of_address_to_resource(np, 0, &res);    \
 226                 io_addr_sprd.id.paddr = res.start;      \
 227                 io_addr_sprd.id.length =                \
 228                         resource_size(&res);            \
 229                 io_addr_sprd.id.vaddr =                 \
 230                 ioremap_nocache(res.start, io_addr_sprd.id.length);\
 231                 pr_debug("sprd io map: phys=%16lx virt=%16lx size=%16lx\n", \
 232         io_addr_sprd.id.paddr, io_addr_sprd.id.vaddr, io_addr_sprd.id.length);\
 233         }                                               \
 234 } while (0)
 235         ADD_SPRD_DEVICE("sprd,ahb", AHB);
 236         ADD_SPRD_DEVICE("sprd,aonapb", AONAPB);
 237         ADD_SPRD_DEVICE("sprd,aonckg", AONCKG);
 238         ADD_SPRD_DEVICE("sprd,apbreg", APBREG);
 239         ADD_SPRD_DEVICE("sprd,core", CORE);
 240         ADD_SPRD_DEVICE("sprd,mmahb", MMAHB);
 241         ADD_SPRD_DEVICE("sprd,pmu", PMU);
 242         ADD_SPRD_DEVICE("sprd,mmckg", MMCKG);
 243         ADD_SPRD_DEVICE("sprd,gpuapb", GPUAPB);
 244         ADD_SPRD_DEVICE("sprd,apbckg", APBCKG);
 245         ADD_SPRD_DEVICE("sprd,gpuckg", GPUCKG);
 246         ADD_SPRD_DEVICE("sprd,int", INT);
 247         ADD_SPRD_DEVICE("sprd,intc0", INTC0);
 248         ADD_SPRD_DEVICE("sprd,intc1", INTC1);
 249         ADD_SPRD_DEVICE("sprd,intc2", INTC2);
 250         ADD_SPRD_DEVICE("sprd,intc3", INTC3);
 251         ADD_SPRD_DEVICE("sprd,uidefuse", UIDEFUSE);
 252         ADD_SPRD_DEVICE("sprd,isp", ISP);
 253         ADD_SPRD_DEVICE("sprd,ca7wdg", CA7WDG);
 254         ADD_SPRD_DEVICE("sprd,csi2", CSI2);
 255         ADD_SPRD_DEVICE("sprd,d-eic-gpio", EIC);
 256         ADD_SPRD_DEVICE("sprd,wdg", WDG);
 257         ADD_SPRD_DEVICE("sprd,ipi", IPI);
 258         ADD_SPRD_DEVICE("sprd,dcam", DCAM);
 259         ADD_SPRD_DEVICE("sprd,syscnt", SYSCNT);
 260         ADD_SPRD_DEVICE("sprd,dma0", DMA0);
 261         ADD_SPRD_DEVICE("sprd,pub", PUB);
 262         ADD_SPRD_DEVICE("sprd,pin", PIN);
 263         ADD_SPRD_DEVICE("sprd,d-gpio-gpio", GPIO);
 264         ADD_SPRD_DEVICE_BY_NAME("hwspinlock0", HWSPINLOCK0);
 265         ADD_SPRD_DEVICE_BY_NAME("hwspinlock1", HWSPINLOCK1);
 266
 267         return 0;
 268 }
 269
 270 static void __init sc8830_init_machine(void)
 271 {
 272         printk("sci get chip id = 0x%x\n", __sci_get_chip_id());
 273
 274         sci_adc_init();
 275 #ifndef CONFIG_MACH_SPX35LFPGA
 276         sci_regulator_init();
 277 #endif
 278         of_sprd_default_bus_lookup[0].phys_addr = 0x20300000;
 279         of_sprd_default_bus_lookup[1].phys_addr = 0x20400000;
 280         of_sprd_default_bus_lookup[2].phys_addr = 0x20500000;
 281         of_sprd_default_bus_lookup[3].phys_addr = 0x20600000;
 282         of_platform_populate(NULL, of_sprd_default_bus_match_table, of_sprd_default_bus_lookup, NULL);
 283         sec_class = class_create(THIS_MODULE, "sec");
 284         if (IS_ERR(sec_class)) {
 285                 pr_err("Failed to create class(sec)!\n");
 286                 printk("Failed create class \n");
 287                 return PTR_ERR(sec_class);
 288         }
 289 }
 290 #ifdef CONFIG_OF
 291 const struct of_device_id of_sprd_late_bus_match_table[] = {
 292         { .compatible = "sprd,sound", },
 293         {}
 294 };
 295 #endif
 296
 297 static void __init sc8830_init_late(void)
 298 {
 299         of_platform_populate(of_find_node_by_path("/sprd-audio-devices"),
 300                                 of_sprd_late_bus_match_table, NULL, NULL);
 301 }
 302
 303
 304 extern void __init sci_enable_timer_early(void);
 305 extern void __init sc_init_chip_id(void);
 306
 307 void __init sprd_init_before_irq(void)
 308 {
 309         iotable_build();
 310         sc_init_chip_id();
 311         /* earlier init request than irq and timer */
 312         __clock_init_early();
 313         /*ipi reg init for sipc*/
 314         sci_glb_set(REG_AON_APB_APB_EB0, BIT_IPI_EB);
 315 }
 316
 317 static void __init sc8830_pmu_init(void)
 318 {
 319         __raw_writel(__raw_readl(REG_PMU_APB_PD_MM_TOP_CFG)
 320                 & ~(BIT_PD_MM_TOP_FORCE_SHUTDOWN),
 321                 REG_PMU_APB_PD_MM_TOP_CFG);
 322
 323         while (__raw_readl(REG_PMU_APB_PWR_STATUS0_DBG) & 0xf0000000) {};
 324
 325         __raw_writel(__raw_readl(REG_PMU_APB_PD_GPU_TOP_CFG)
 326                 & ~(BIT_PD_GPU_TOP_FORCE_SHUTDOWN),
 327                 REG_PMU_APB_PD_GPU_TOP_CFG);
 328
 329         while (__raw_readl(REG_PMU_APB_PWR_STATUS0_DBG) & 0x0f000000) {};
 330
 331         __raw_writel(__raw_readl(REG_AON_APB_APB_EB0) | BIT_MM_EB |
 332                 BIT_GPU_EB, REG_AON_APB_APB_EB0);
 333         __raw_writel(__raw_readl(REG_MM_AHB_AHB_EB) | BIT_MM_CKG_EB,
 334                 REG_MM_AHB_AHB_EB);
 335         __raw_writel(__raw_readl(REG_MM_AHB_GEN_CKG_CFG)
 336                 | BIT_MM_MTX_AXI_CKG_EN | BIT_MM_AXI_CKG_EN,
 337                 REG_MM_AHB_GEN_CKG_CFG);
 338         __raw_writel(__raw_readl(REG_MM_CLK_MM_AHB_CFG) | 0x3,
 339                 REG_MM_CLK_MM_AHB_CFG);
 340 }
 341
 342 static void sprd_init_time(void)
 343 {
 344         if (of_have_populated_dt()) {
 345                 sc8830_pmu_init();
 346                 of_clk_init(NULL);
 347                 clocksource_of_init();
 348         } else {
 349                 sci_clock_init();
 350                 sci_enable_timer_early();
 351                 sci_timer_init();
 352         }
 353 }
 354 static const char *sprd_boards_compat[] __initdata = {
 355         "sprd,sp8835eb",
 356         NULL,
 357 };
 358 extern struct smp_operations sprd_smp_ops;
 359
 360 MACHINE_START(SCPHONE, "sc8830")
 361         .smp            = smp_ops(sprd_smp_ops),
 362         .reserve        = sci_reserve,
 363         .map_io         = sci_map_io,
 364         .init_irq       = sci_init_irq,
 365         .init_time      = sprd_init_time,
 366         .init_machine   = sc8830_init_machine,
 367         .init_late      = sc8830_init_late,
 368         .dt_compat      = sprd_boards_compat,
 369 MACHINE_END
 370